Sensor readout detector circuit

• US 5,793,230 A
• Filed: 02/26/1997
• Issued: 08/11/1998
• Est. Priority Date: 02/26/1997
• Status: Expired due to Term

• Current Assignee: Sandia Corporation (Martin Marietta Corporation)
• Original Assignee: Sandia Corporation (Martin Marietta Corporation)
• Inventors: Thelen, Donald C. Jr., Chu, Dahlon D.
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US08/806,950
• Time in Patent Office: 531 Days
• Field of Search: 327/77, 327/78, 327/79, 327/103, 327/337, 327/554, 327/362, 327/363, 327/514, 327/509, 327/87, 327/307, 330/259, 330/290
• US Class Current: 327/77
• CPC Class Codes: G01N 27/4148 Integrated circuits therefor, e.g. fabricated by CMOS processing CMOS processing per se H01L21/82
• CPC Class Codes: H03F 3/087 with IC amplifier blocks H03F3/085 takes precedence
• CPC Class Codes: H03K 5/007 Base line stabilisation thresholding H03K5/08
• CPC Class Codes: H03K 5/08 by limiting; by thresholding; by slicing, i.e. combined limiting and thresholding H03K5/07 takes precedence; comparing one pulse with another H03K5/22; providing a determined threshold for switching H03K17/30
• CPC Class Codes: H03K 5/2481 with at least one differential stage

Abstract

A sensor readout detector circuit is disclosed that is capable of detecting sensor signals down to a few nanoamperes or less in a high (microampere) background noise level. The circuit operates at a very low standby power level and is triggerable by a sensor event signal that is above a predetermined threshold level. A plurality of sensor readout detector circuits can be formed on a substrate as an integrated circuit (IC). These circuits can operate to process data from an array of sensors in parallel, with only data from active sensors being processed for digitization and analysis. This allows the IC to operate at a low power level with a high data throughput for the active sensors. The circuit may be used with many different types of sensors, including photodetectors, capacitance sensors, chemically-sensitive sensors or combinations thereof to provide a capability for recording transient events or for recording data for a predetermined period of time following an event trigger. The sensor readout detector circuit has applications for portable or satellite-based sensor systems.

Claims

1. A readout detector circuit for processing an electrical current signal from at least one sensor, comprising:

(a) means for receiving the electrical current signal from each sensor and converting the electrical signal to a voltage signal;

(b) means for amplifying the voltage signal;

(c) means, connected between the amplifying means and the receiving means, for receiving the amplified voltage signal and removing direct-current and low-frequency noise components from the amplified voltage signal; and

(d) means for receiving the amplified voltage signal and detecting signals of interest above a predetermined threshold level.

2. The readout detector circuit in claim 1 wherein the means for converting the electrical current signal to a voltage signal comprises a transimpedance amplifier.

3. The readout detector circuit in claim 2 wherein the transimpedance amplifier comprises a current-buffered transimpedance amplifier.

4. The readout detector circuit in claim 1 wherein the means for amplifying the voltage signal includes means for low-pass filtering the voltage signal.

5. The readout detector circuit in claim 1 wherein the means for removing direct-current and low-frequency noise components from the voltage signal comprises a switched-capacitor integrator.

6. The readout detector circuit in claim 5 wherein the switched-capacitor integrator is an offset-cancelling or differential switched-capacitor integrator.

7. The readout detector circuit in claim 5 wherein the switched-capacitor integrator has a unity gain frequency in the range of 10-100 Hz and is clocked at a frequency in the range of 1-10 KHz.

8. The readout detector circuit in claim 1 wherein the means for detecting signals of interest above a predetermined threshold level includes an auto-zeroed comparator having an adjustable input threshold level.

9. The readout detector circuit in claim 8 wherein the means for detecting signals of interest above a predetermined threshold level provides output signals to an analog-to-digital converter only when the signals of interest are above the threshold level.

10. The readout detector circuit in claim 1 wherein the sensors are selected from the group consisting of photodetectors, capacitance sensors, chemically-sensitive sensors, or combinations thereof.

11. The readout detector circuit in claim 1 in the form of an integrated circuit.

12. The readout detector circuit in claim 11 wherein the integrated circuit further includes the at least one sensor.

13. The readout detector circuit in claim 12 wherein the sensors are selected from the group consisting of photodetectors, capacitance sensors, chemically-sensitive sensors, or combinations thereof.

14. A readout detector circuit for processing an electrical current signal from at least one sensor, comprising:

(a) a transimpedance amplifier for converting the electrical current signal to a voltage signal;

(b) a voltage amplifier for amplifying the voltage signal;

(c) a switched capacitor integrator for providing feedback from the voltage amplifier to the transimpedance amplifier for removing direct-current and low-frequency noise components from the voltage signal; and

(d) an auto-zeroed comparator for providing an indication when the amplified voltage signal is above a predetermined threshold level.

15. The readout detector circuit of claim 14 wherein the transimpedance amplifier comprises a current-buffered transimpedance amplifier.

16. The readout detector circuit of claim 15 wherein the current-buffered transimpedance amplifier lacks a differential pair and feedback resistors.

17. The readout detector circuit of claim 14 wherein the voltage amplifier includes a low-pass filter.

18. The readout detector circuit of claim 14 wherein the switched capacitor integrator is an offset-cancelling or differential switched-capacitor integrator.

19. The readout detector circuit of claim 14 wherein the switched capacitor integrator has a unity gain frequency in the range of 10-100 Hz and is clocked at a frequency in the range of 1-10 KHz.

20. The readout detector circuit of claim 14 wherein the auto-zeroed comparator includes an adjustable threshold level.

21. The readout detector circuit of claim 14 wherein the auto-zeroed comparator is operatively connected to signal an analog-to-digital converter to digitize signal data.

22. The readout detector circuit of claim 14 in the form of an integrated circuit.

23. The readout detector circuit in claim 22 wherein the integrated circuit further includes the at least one sensor.

24. A method of detecting signals of interest from at least one sensor, the method comprising the steps of:

(a) converting by transimpedance amplifier an electrical current signal from each sensor to a voltage signal;

(b) amplifying the voltage signal;

(c) removing direct-current and low-frequency noise components from the voltage signal by integrating the amplified voltage signal and feeding back the integrated signal to the transimpedance amplifier; and

(d) detecting signals of interest by an auto-zeroed comparator.

25. The method of claim 24 wherein the converting step comprises converting by an operational amplifier.

26. The method of claim 24 wherein the converting step comprises converting by a current-buffered transimpedance amplifier lacking a differential pair and feedback resistors.

27. The method of claim 24 wherein the amplifying step further includes a step of low-pass filtering the voltage signal.

28. The method of claim 25 wherein the amplifying step comprises utilizing a unity gain frequency in the range of 10-100 Hz.

29. The method of claim 24 wherein the removing step comprises clocking at 1-10 KHz.

30. The method of claim 29 wherein the removing step comprises a step of stopping the clocking for a predetermined period of time upon detecting signals of interest.

31. The method of claim 30 wherein the step of stopping the clock for a predetermined time upon detecting signals of interest results in holding the integrated signals in the removing step at a substantially constant level for the predetermined period of time.

32. The method of claim 24 wherein the detecting step comprises providing an adjustable threshold level to the auto-zeroed comparator, and further includes a step of digitizing the signals of interest by an analog-to-digital converter.