System for preventing of crosstalk between a raw digital output signal and an analog input signal in an analog-to-digital converter

• US 5,793,318 A
• Filed: 02/05/1997
• Issued: 08/11/1998
• Est. Priority Date: 02/05/1997
• Status: Expired due to Term

• Current Assignee: Keysight Technologies, Inc.
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Jewett, Robert E.
• Primary Examiner(s): Elms, Richard T.
• Assistant Examiner(s): HUYNH, KIM NGOC
• Application Number:
  US08/795,220
• Time in Patent Office: 552 Days
• Field of Search: 341/89, 341/118, 341/143, 341/155
• US Class Current: 341/118
• CPC Class Codes: H03M 1/0641 the dither being a random signal
• CPC Class Codes: H03M 1/0827 of electromagnetic or electrostatic field noise, e.g. preventing crosstalk by shielding or optical isolation
• CPC Class Codes: H03M 1/12 Analogue/digital converters H03M1/001 – H03M1/10 take precedence

Abstract

The raw digital output signal generated at the transmitter by an ADC is XOR'"'"'d with a sequence of pseudo-random numbers to generate an encoded output signal. This removes all correlation between the analog input signal and the encoded output signal. Coherence between the encoded output signal and the analog input signal is prevented and the effects of crosstalk to the analog input signal are mitigated. In a first embodiment of the invention, the sequence of pseudo-random numbers is a sequence of one-bit pseudo-random numbers that are XOR'"'"'d with each bit of the raw digital output signal. In a second embodiment, the sequence of pseudo-random numbers is a sequence of N-bit pseudo-random numbers that are XOR'"'"'d with the N-bit words of the digital output signal. To recreate the original raw digital output signal in the receiver, a second XOR operation is performed between the encoded output signal and the sequence of pseudo-random numbers. Alternatively, a pseudo-random number generator located in each of the transmitter and receiver are synchronized to generate equal sequences of PRNs that encode the raw digital output signal and decode the encoded output signal. Intermediate digital pipelining may be used to add a decoding bit from the pseudo-random-number generator to the encoded output signal. Such additional bit may be stored in memory with the encoded output signal to permit later decoding.

Claims

1. A method for preventing crosstalk between a raw digital output signal and an analog input signal in an analog-to-digital converter, the method comprising the steps of:

transmitting the raw digital output signal to a first XOR gate;

generating a first pseudo-random number; and

performing an XOR operation at the first XOR gate between the raw digital output signal and the first pseudo-random number to generate an encoded output signal.

2. The method of claim 1, in which each pseudo-random number in the first sequence of pseudo-random numbers consists of a single bit.

3. The method of claim 1, in which the first sequence of pseudo-random numbers comprises N-bit words.

4. The method of claim 1, in which the step of generating a first sequence of pseudo-random numbers includes the steps of:

providing a linear feedback shift register; and

using the linear feedback shift register to generate the first sequence of pseudo-random numbers.

5. The method of claim 1, further comprising a step of performing an XOR operation on the encoded output signal at a second XOR gate to re-generate the raw digital output signal.

6. The method of claim 5, in which the XOR operation at the second XOR gate is performed between the encoded output signal and the first sequence of pseudo-random numbers.

7. The method of claim 5, in which:

the first sequence of pseudo-random numbers is generated in response to a synchronizing signal;

the method additionally comprises a step of generating a second sequence of pseudo-random numbers, identical to the first sequence of pseudo-random numbers, in response to the synchronizing signal; and

in the step of performing the second XOR operation, the second XOR operation is performed using the second sequence of pseudo-random numbers.

8. The method of claim 1, further comprising a step of storing at least one of the first sequence of pseudo-random numbers, the second sequence of pseudo-random numbers and the encoded output signal.

9. The method of claim 1, further comprising steps of:

latching an output of the XOR operation at the first XOR gate;

conveying the latched XOR output to at least one output driver; and

synchronizing the analog-to-digital conversion and the latched XOR output to the at least one output driver.

10. A system for preventing crosstalk between a raw digital output signal and an analog input signal in an analog-to-digital converter having an analog input signal and a raw digital output signal, comprising:

means for generating a first pseudo-random number;

first XOR gate means for receiving the raw digital output signal and for performing an XOR operation between the raw digital output signal and the first pseudo-random number to generate an encoded output signal.

11. The system of claim 10, in which each pseudo-random number in the first sequence of pseudo-random numbers consists of a single bit.

12. The system of claim 10, in which the first sequence of pseudo-random numbers comprises N-bit words.

13. The system of claim 10, in which the means for generating a first sequence of pseudo-random numbers comprises a linear feedback shift register.

14. The system of claim 10, further comprising means for regenerating the raw digital output signal.

15. The system of claim 14, in which the means for regenerating the raw digital output signal includes a second XOR gate.

16. The system of claim 14, in which the second XOR gate is configured to perform an XOR operation with the encoded output signal and the first pseudo-random number to re-generate the raw digital output signal.

17. The system of claim 10, further comprising:

means for generating a second sequence of pseudo-random numbers; and

means for synchronizing the means for generating the second sequence of pseudo-random numbers with the means for generating the first sequence of pseudo-random numbers.

18. The system of claim 17, in which the means for generating the second sequence of pseudo-random numbers is a linear feedback shift register.

19. The system of claim 12, further comprising memory means for storing at least one of the first sequence of pseudo-random numbers, the second sequence of pseudo-random numbers, and the encoded output signal.

20. The system of claim 12, further comprising:

at least one latch for latching an output of the XOR operation at the first XOR gate;

at least one output driver for receiving the latched XOR output; and

a synchronizer for synchronizing the analog-to-digital converter and the latched XOR output to the at least one output driver.