Dynamic refinement of pixels for a display

• US 5,793,345 A
• Filed: 03/13/1995
• Issued: 08/11/1998
• Est. Priority Date: 03/11/1994
• Status: Expired due to Fees

• Current Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Original Assignee: Canon Kabushiki Kaisha (Canon Inc.)
• Inventors: Silverbrook, Kia
• Primary Examiner(s): Saras, Steven
• Assistant Examiner(s): LEWIS, DAVID LEE
• Application Number:
  US08/402,496
• Time in Patent Office: 1,247 Days
• Field of Search: 345/88, 345/89, 345/97, 345/98, 345/100, 345/103, 345/147, 345/149, 345/152, 357/56
• US Class Current: 345/89
• CPC Class Codes: G02F 1/133514 Colour filters
• CPC Class Codes: G02F 1/134309 characterised by their geometrical arrangement
• CPC Class Codes: G02F 1/134345 Subdivided pixels, e.g. for grey scale or redundancy
• CPC Class Codes: G09G 2310/04 Partial updating of the display screen
• CPC Class Codes: G09G 2320/041 Temperature compensation
• CPC Class Codes: G09G 2340/0407 Resolution change, inclusive of the use of different resolutions for different screen areas
• CPC Class Codes: G09G 2340/0457 Improvement of perceived resolution by subpixel rendering
• CPC Class Codes: G09G 2370/045 using multiple communication channels, e.g. parallel and serial
• CPC Class Codes: G09G 3/2074 using sub-pixels
• CPC Class Codes: G09G 3/3607 for displaying colours or for displaying grey scales with a specific pixel layout, e.g. using sub-pixels display of colours in flat matrix panels other than liquid crystal displays G09G3/2003; grey scales specific for television H04N3/127
• CPC Class Codes: G09G 3/364 with use of subpixels
• CPC Class Codes: G09G 3/3681 suitable for passive matrices only
• CPC Class Codes: G09G 3/3692 suitable for passive matrices only
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: G09G 5/42 characterised by the display of patterns using a display memory without fixed position correspondence between the display memory contents and the display position on the screen

Abstract

Due to increasing resolution of display technology, it is necessary to drive an individual line of a display at an ever increasing rate. The present invention discloses a display having a pixel arrangement (1, 70) which can be driven in a number of different modes. In a first mode, substantially all of the common lines (55, 71-73) of a line of pixels are simultaneously driven. In a second mode the common lines (55, 71-73) of the display are driven independently. This allows a single line of a display, having a pixel arrangement as disclosed, to be driven at a number of different speeds depending on the necessary speed of update. Particular examples are disclosed with reference to a ferroelectric liquid crystal form of display.

Claims

1. A discrete level display having a plurality of pixels, each said pixel having a plurality of drive lines and a plurality of common lines, said display having at least two pixel update states including:

a motion update state wherein a plurality of said common lines of said pixels are able to be driven in unison; and

a refining update state wherein said common lines of said pixels are able to be driven independently.

2. A discrete level display as claimed in claim 1, wherein each pixel has a predetermined number of primary color components and said plurality of drive lines are divided into groups of drive lines for each primary color component.

3. A discrete level display as claimed in claim 2, wherein the drive lines for each primary color component are connected to sub-pixel portions of each said pixel and wherein when said display is in a motion update state, said drive lines drive said sub-pixel portions such that a ratio of the areas or luminance of which form a substantially binary ratio.

4. A discrete level display as claimed in claim 3, wherein, when said display is in said refining update state, each of said drive lines and corresponding said plurality of common lines drive an area or luminance having a substantially binary ratio.

5. A discrete level display as claimed in claim 2, wherein said drive lines for each primary color component are allocated substantially in accordance with the luminance of said primary color component.

6. A discrete level display as claimed in claim 3, wherein said sub-pixel portions of said pixels to which said drive lines connect are substantially optically centered.

7. A discrete level display as claimed in claim 2, wherein said primary color components are red, green and blue.

8. A discrete level display as claimed in any one of claims 1 to 7, wherein said display is a ferro electric liquid crystal display.

9. A discrete level display as claimed in any one of claims 1 to 7, wherein said display is a back light display.

10. A method of updating a discrete level display, the display having a plurality of pixels, each pixel having a plurality of drive lines and a plurality of common lines, said method comprising the steps of:

entering a motion update state when motion in the pixels of an input image in excess of a first predetermined minimum motion is detected and driving a plurality of the common lines corresponding to the pixels in unison; and

entering a refinement update state when motion less than a second predetermined minimum motion is detected and refreshing the pixels by driving the common lines independently.

11. A method of updating a discrete level display as claimed in claim 10, further comprising the step of entering a background refresh state of driving all the pixels of the display once said refreshing is completed.

12. A method as claimed in claim 10 or 11, wherein the pixels comprise a plurality of independently illuminable areas and the number of the areas able to be independently illuminated in the motion update state is less than the number of the areas able to be independently illuminated in the refinement update state.

13. A discrete level display comprising:

a plurality of pixels each having connected thereto a plurality of drive lines and a plurality of common lines;

means for driving a plurality of said common lines in unison to define a motion update state of said display; and

means for driving a plurality of said common lines independently to define a refining update state of said display.

14. A memory characteristic display having a plurality of pixels, each said pixel having a plurality of sub-pixels having a different scale, and having a plurality of common lines and drive lines each provided corresponding to each said sub-pixel, said display comprising:

means for entering a first mode of simultaneously driving each of said plurality of common lines connected to each said pixel when motion occurs in an image input to said display;

means for entering a second mode of independently driving each of said plurality of common lines connected to each said pixel updated in the first mode when an amount of motion of the input image is below the predetermined threshold; and

means for entering a third mode of individually driving all of said plurality of common lines connected to said plurality of pixels in a determined sequence from the time when the motion of the input image has ceased until a time when the motion occurs again.

15. A memory characteristic display as claimed in claim 14, wherein one of said plurality of common lines is connected to one of said plurality of sub-pixels which is provided on a plurality of lines, and wherein another of said plurality of common lines is connected to one of said plurality of sub-pixels which is provided between said plurality of lines.

16. A memory characteristic display as claimed in claim 14 or 15, wherein said display is ferroelectric liquid crystal display.