Image decoder with bus arbitration circuit

• US 5,793,384 A
• Filed: 02/05/1996
• Issued: 08/11/1998
• Est. Priority Date: 02/09/1995
• Status: Expired due to Fees

• Current Assignee: Yamaha Corporation
• Original Assignee: Yamaha Corporation
• Inventors: Okitsu, Hiromi
• Primary Examiner(s): Bayerl, Raymond J.
• Assistant Examiner(s): Nguyen, Cao H.
• Application Number:
  US08/596,737
• Time in Patent Office: 918 Days
• Field of Search: 382/232, 382/233, 395/511, 395/501, 395/512
• US Class Current: 345/535
• CPC Class Codes: G06F 13/364 using independent requests or grants, e.g. using separated request and grant lines
• CPC Class Codes: G09G 2340/02 Handling of images in compressed format, e.g. JPEG, MPEG
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/363 Graphics controllers

Abstract

An image decoder has a bus arbitrating circuit for controlling the use of the bus by any one of input bit stream buffer control circuit, decoding circuit, and image output control circuit. The bus arbitrating circuit controls the bus to provide the image output control means with the highest priority to use the bus without interruption to access the memory at predetermined time intervals. After the completion of the memory access by the image output control means, the bus arbitrating circuit detects whether a request for access to the memory is made by the input bit stream buffer control circuit, and when the request is made, permits the input bit stream buffer control circuit to use the bus. When both the image output control circuit and input bit stream buffer control circuit are not using the bus, permits the decoding means to use the bus to access the memory.

Claims

1. An image decoder for decoding an input bit stream, the image decoder comprising:

a memory having

an input bit stream buffer for storing the input bit stream;

an image memory region for storing a decoded image; and

an image decoding circuit coupled to the memory through a bus, the image decoding circuit having

input bit stream buffer control means coupled to the bus for writing and reading the input bit stream to and from the input bit stream buffer;

decoding means coupled to the bus for reading the input bit stream from the input bit stream buffer to generate decoded image data, and for writing the decoded image data in the image memory region;

image output control means coupled to the bus for reading the decoded image data from the image memory region and outputting the decoded image data; and

bus arbitrating means coupled to at least one of the input bit stream buffer control means, the decoding means and the image output control means for controlling use of the bus by any one of the input bit stream buffer control means, decoding means, and image output control means, wherein the bus arbitrating means controls the bus to provide the image output control means with the highest priority to use the bus without interruption to access the memory at predetermined time intervals, and after the completion of the memory access by the image output control means, detects whether a request for access to the memory is made by the input bit stream buffer control means, and when the request is made, permits the input bit stream buffer control means to use the bus, and when both the image output control means and input bit stream buffer control means are not using the bus, permits the decoding means to use the bus to access the memory.

2. The image decoder according to claim 1, wherein the decoding means reads the decoded image, as a reference image, from the image memory region, and based on the reference image, decodes the input bit stream from the input bit stream buffer control means using an inter-frame motion compensation.

3. An image decoding circuit for decoding an input bit stream, operable with a memory device having an input bit stream buffer and an image memory region, the image decoding circuit coupled to the memory device via a bus, the image decoding circuit comprising:

input bit stream buffer control means coupled to the bus for writing and reading the input bit stream to and from the input bit stream buffer;

decoding means coupled to the bus for reading the input bit stream from the input bit stream buffer to generate decoded image data, and for writing the decoded image data in the image memory region;

image output control means coupled to the bus for reading the decoded image data from the image memory region and outputting the decoded image data; and

bus arbitrating means coupled to at least one of the input bit stream buffer control means, the decoding means and the image output control means for controlling use of the bus by any one of the input bit stream buffer control means, decoding means, and image output control means, wherein the bus arbitrating means controls the bus to provide the image output control means with the highest priority to use the bus without interruption to access the memory at predetermined time intervals, and after the completion of the memory access by the image output control means, detects whether a request for access to the memory is made by the input bit stream buffer control means, and when the request is made, permits the input bit stream buffer control means to use the bus, and when both the image output control means and input bit stream buffer control means are not using the bus, permits the decoding means to use the bus to access the memory.

4. An image decoding circuit according to claim 3, wherein the bus arbitrating means includes:

a first input signal generated from the image output control means;

a second input signal generated from the input bit stream buffer control means;

a third input signal generated from the decoding means;

a first output signal provided to the image output control means;

a second output signal provided to the input bit stream control means; and

a third output signal provided to the decoding means,

wherein when the first input signal is activated, the first output signal is accordingly activated for the image output control means to access the bus without interruption and the second and the third output signals are deactivated,

when the second input signal is activated, the second output signal is activated for the input bit stream buffer control means to access the bus only when the first input signal has been deactivated, and

when the third input signal is activated, the third output signal is activated for the decoding means to access the bus only when both the first and the second input signals have been deactivated.

5. An image decoding circuit for decoding an input bit signal, operable with a memory device having an input bit stream buffer and an image memory, the image decoding circuit coupled to the memory device via a bus, the image decoding circuit comprising:

an input bit stream buffer control unit coupled to the bus for writing and reading the input bit signal to and from the input bit stream buffer;

a decoding unit coupled to the bus for reading the input bit signal from the input bit stream buffer to generate decoded image data, and for writing the decoded image data in the image memory;

an image output control unit coupled to the bus for reading the decoded image data from the image memory and outputting the decoded image data; and

a bus arbitrating unit coupled to at least one of the input bit stream buffer control means, the decoding means and the image output control means for controlling use of the bus by any one of the input bit stream buffer control unit, decoding unit, and image output control unit, wherein the bus arbitrating means controls the bus to provide the image output control unit with the highest priority to use the bus without interruption to access the memory at predetermined time intervals, and after the completion of the memory access by the image output control unit, detects whether a request for access to the memory is made by the input bit stream buffer control unit, and when the request is made, permits the input bit stream buffer control unit to use the bus, and when both the image output control unit and input bit stream buffer control unit are not using the bus, permits the decoding unit to use the bus to access the memory.