Image control device for use in a video multiplexing system for superimposition of scalable video data streams upon a background video data stream

• US 5,793,439 A
• Filed: 02/20/1997
• Issued: 08/11/1998
• Est. Priority Date: 07/13/1988
• Status: Expired

• Current Assignee: Seiko Epson Corporation (Seiko Group)
• Original Assignee: Seiko Epson Corporation (Seiko Group)
• Inventors: Takeuchi, Kesatoshi
• Primary Examiner(s): Kostak, Victor R.
• Application Number:
  US08/803,227
• Time in Patent Office: 537 Days
• Field of Search: 348/584, 348/564, 348/581, 348/586, 348/588, 348/598, 348/600, 348/714-716, 348/718, 345/200, 345/113, 345/115
• US Class Current: 348/584
• CPC Class Codes: G09G 1/167 Details of the interface to the display terminal specific for a CRT details suitable for both CRT and flat panel G09G5/006, specific for a flat panel G09G3/2096
• CPC Class Codes: G09G 2340/0435 Change or adaptation of the frame rate of the video stream
• CPC Class Codes: G09G 2340/125 wherein one of the images is motion video
• CPC Class Codes: G09G 2360/02 Graphics controller able to handle multiple formats, e.g. input or output formats
• CPC Class Codes: G09G 2360/126 The frame memory having additional data ports, not inclusive of standard details of the output serial port of a VRAM
• CPC Class Codes: G09G 5/001 Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
• CPC Class Codes: G09G 5/008 Clock recovery
• CPC Class Codes: G09G 5/14 Display of multiple viewports
• CPC Class Codes: G09G 5/363 Graphics controllers
• CPC Class Codes: G09G 5/39 Control of the bit-mapped memory
• CPC Class Codes: G09G 5/393 Arrangements for updating the contents of the bit-mapped memory
• CPC Class Codes: G09G 5/395 Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen G09G5/399 takes precedence
• CPC Class Codes: H04N 21/4143 embedded in a Personal Computer [PC]
• CPC Class Codes: H04N 21/426 Internal components of the client ; Characteristics thereof H04N5/44 takes precedence
• CPC Class Codes: H04N 5/44 Receiver circuitry for the reception of television signals according to analogue transmission standards H04N5/14 takes precedence
• CPC Class Codes: H04N 5/44504 Circuit details of the additional information generator, e.g. details of the character or graphics signal generator, overlay mixing circuits
• CPC Class Codes: H04N 5/45 Picture in picture , e.g. displaying simultaneously another television channel in a region of the screen
• CPC Class Codes: H04N 9/641 Multi-purpose receivers, e.g. for auxiliary information H04N9/642 takes precedence

Abstract

An image control device for use in a computer system which includes a microprocessor, a bus coupled to the microprocessor, a video memory coupled to the bus and a display device. A write controller is also provided which is coupled to the bus and which controls writing of an image signal into the video memory by supplying a write address to the video memory. The write controller operates to change a range of the write address according to a plurality of write address parameters set by the microprocessor so that a memory area of the video memory into which the image signal is to be written is changed according to the range of the write address. Further, a size of an image represented by the image signal to be written into the video memory is changed. A read controller is also provided and is coupled to the bus for controlling reading of an image signal out of the video memory by supplying a read address to the video memory asynchronously with the writing into the video memory, and in synchronism with the synchronizing signal supplied to the display device along with the image signal read out of the video memory.

Claims

1. An image control device for use in a computer system having a microprocessor, a bus coupled to said microprocessor, a video memory coupled to said bus, and a display device, said image control device comprising:

write control means coupled to said bus for controlling the writing of an image signal into said video memory by supplying a write address to said video memory; and

first read control means coupled to said video memory and said display device, for controlling the reading of an image signal of a motion picture out of said video memory in synchronism with a synchronizing signal which is supplied to said display device along with said motion picture image signal; and

second read control means coupled to said video memory and said bus, for controlling the reading of an image signal out of said video memory while said first read control means executes the reading of said motion picture image signal.

2. An image control device in accordance with claim 1, further comprising:

a first output buffer, coupled to said video memory and said display device, for temporarily storing said motion picture image signal read out of said video memory before transferring said motion picture image signal to said display device; and

a second output buffer, coupled to said video memory and said bus, for temporarily storing said image signal read out of said video memory before transferring said image signal to said microprocessor.

3. A computer system comprising:

a microprocessor;

a bus coupled to said microprocessor;

a video memory coupled to said bus;

a display device;

write control means coupled to said bus for controlling the writing of an image signal into said memory by supplying a write address to said video memory;

first read control means coupled to said video memory and said display device, for controlling the reading of an image signal of a motion picture out of said video memory in synchronism with a synchronizing signal which is supplied to said display device along with said motion picture image signal; and

second read control means coupled to said video memory and said bus, for controlling the reading of an image signal out of said video memory while said first read control means executes the reading of said motion picture image signal.

4. A computer system in accordance with claim 3, further comprising:

a first output buffer, coupled to said video memory and said display device, for temporarily storing said motion picture image signal read out of said memory before transferring said motion picture image signal to said display device; and

a second output buffer, coupled to said video memory and said bus, for temporarily storing said image signal read out of said video memory before transferring said image signal to said microprocessor.