Low power register memory element circuits

• US 5,793,672 A
• Filed: 03/11/1997
• Issued: 08/11/1998
• Est. Priority Date: 03/11/1997
• Status: Expired due to Term

• Current Assignee: GlobalFoundries, Inc.
• Original Assignee: Advanced Micro Devices, Inc.
• Inventors: Khou, Beng Chew, Wong, Jacques Ah Miow, Aspacio, Reuben A.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): NGUYEN, HIEN N
• Application Number:
  US08/814,397
• Time in Patent Office: 518 Days
• Field of Search: 365/154, 365/189.05, 365/227, 365/230.08
• US Class Current: 365/154
• CPC Class Codes: G11C 7/1078 Data input circuits, e.g. write amplifiers, data input buffers, data input registers, data input level conversion circuits
• CPC Class Codes: G11C 7/1093 Input synchronization

Abstract

A flip-flop for storing a bit of digital information generally used in register architectures is comprised of a two-input NAND gate and a D-type flip-flop. The output of the NAND gate is connected to the clock terminal of the flip-flop and the data signal is directed to the data terminal of the flip-flop. A new clock scheme is provided with for this circuit configuration in order to properly store the data signal.

Claims

1. A low power memory circuit comprising:

a NAND gate having a first input terminal for receiving an input write-enable signal, a second input terminal for receiving a clock signal, and an output terminal upon which a control signal is generated as a function of said input write-enable signal and said clock signal; and

a flip-flop having a data terminal for receiving a data signal, a clock terminal connected to said output terminal of said NAND gate for receiving said control signal, and a data output terminal.

2. A low power memory circuit as recited in claim 1 wherein said flip-flop is operated to latch said data signal appearing on said data terminal when said control signal at said clock terminal is low.

3. A low power memory circuit as recited in claim 2 wherein to latch said data signal said control signal is low within a duration when said data signal is high.

4. A low power memory circuit as recited in claim 2 wherein to latch said data signal said control signal is low within a duration when said data signal is low.

5. A low power memory circuit as recited in claim 1 wherein said flip-flop is a D-type flip-flop.

6. A low power memory circuit as recited in claim 1 wherein a plurality of the low power memory circuits forms a register for receiving and storing multiple digital data values.

7. A low power memory circuit as recited in claim 1 wherein said clock signal is provided by a clock generator and said data signal is provided by a data generator.

8. A low power memory circuit as recited in claim 7 wherein in latching said data signal said clock generator generating said clock signal at an interval having a pre-determined relationship with said data signal.

9. A low power memory circuit as recited in claim 8 wherein when said data signal is latched in said flip-flop when said control signal is low.

10. A low power memory circuit as recited in claim 8 wherein said control signal is low when said write-enable signal and said clock signal are high.

11. A low power memory circuit as recited in claim 8 wherein said clock generator causes said clock signal to go high within an interval when said data signal does not change state.

12. A memory circuit comprising:

a NAND gate having a first input terminal for receiving a write-enable signal, a second input terminal for receiving a clock signal, and an output terminal for generating a control signal in response to said write-enable signal and said clock signal;

a flip-flop having a data input terminal for receiving a data signal, a clock terminal connected to said output terminal of said NAND gate for receiving said control signal; and

said memory circuit latches said data signal when said control signal is low.

13. A memory circuit as recited in claim 12 where said flip-flop is a D-type flip-flop.

14. A memory circuit as recited in claim 12 wherein a plurality of the circuits forms a register for receiving and storing multiple digital data values.

15. A memory circuit as recited in claim 12 wherein said clock signal is provided by a clock generator and said data signal is provided by a data generator.

16. A memory circuit as recited in claim 15 wherein in latching said data signal said clock generator generating said clock signal at an interval having a pre-determined relationship with said data signal.

17. A memory circuit as recited in claim 16 wherein said control signal is low when said write-enable signal and said clock signal are high.

18. A memory circuit as recited in claim 16 wherein said clock generator causes said clock signal to go high within an interval when said data signal does not change state.