Non-volatile semiconductor memory device and memory system using the same

• US 5,793,696 A
• Filed: 04/08/1997
• Issued: 08/11/1998
• Est. Priority Date: 12/19/1991
• Status: Expired due to Term

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Aritome, Seiichi, Kato, Hideo, Tanaka, Yoshiyuki, Tanaka, Tomoharu, Nakamura, Hiroshi, Shirota, Riichiro, Iwata, Yoshihisa, Nakai, Hiroto, Okamoto, Yutaka, Momodomi, Masaki, Asano, Masamichi, Tokushige, Kaoru, Odaira, Hideko, Itoh, Yasuo
• Primary Examiner(s): Fears, Terrell W.
• Application Number:
  US08/826,820
• Time in Patent Office: 490 Days
• US Class Current: 365/230.06
• CPC Class Codes: G06F 11/1008 in individual solid state devices G06F11/1004 takes precedence
• CPC Class Codes: G06F 11/1068 in sector programmable memories, e.g. flash disk G06F11/1072 takes precedence
• CPC Class Codes: G06F 2201/81 Threshold
• CPC Class Codes: G06F 2212/2022 Flash memory
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/12 Programming voltage switching circuits
• CPC Class Codes: G11C 16/24 Bit-line control circuits
• CPC Class Codes: G11C 16/3436 Arrangements for verifying correct programming or erasure
• CPC Class Codes: G11C 16/344 Arrangements for verifying correct erasure or for detecting overerased cells
• CPC Class Codes: G11C 16/3454 Arrangements for verifying correct programming or for detecting overprogrammed cells
• CPC Class Codes: G11C 29/34 Accessing multiple bits simultaneously
• CPC Class Codes: G11C 29/52 Protection of memory contents; Detection of errors in memory contents
• CPC Class Codes: G11C 29/785 with redundancy programming schemes

Abstract

The time required for the program verify and erase verify operations can be shortened. The change of threshold values of memory cells can be suppressed even if the write and erase operations are executed repetitively. After the program and erase operations, whether the operations were properly executed can be judged simultaneously for all bit lines basing upon a change, after the pre-charge, of the potential at each bit line, without changing the column address. In the data rewrite oepration, the rewrite operation is not effected for a memory cell with the data once properly written, by changing the data in the data register.

Claims

1. A non-volatile semiconductor memory system comprising:

a plurality of memory cells arranged into substantially a matrix pattern to construct a memory cell array, data being electrically erasable from and writable in each of said memory cells;

a plurality of bit lines each connected to said memory cells, each for transmitting a voltage corresponding to data to be written to one of said memory cells in which data are to be written in write mode and for receiving a voltage corresponding to data to be read from one of said memory cells from which data are to be read in read mode;

a plurality of data storing circuits each connected to each of said bit lines, for storing data to be written;

in the write mode, the written data controlling voltage of said bit lines; and

when data are read for write verify, levels of the data to be written and stored in said data storing circuits being determined, on the basis of the data read from said memory cells to which data have been already written, so that data can be written in only said memory cells to which data have not been properly written;

a plurality of data detecting circuits each connected to a predetermined number of said data storing circuits, each for detecting data stored in each of said data storing circuits and outputting the detected data when data are read for write verify; and

a write end detecting circuit for receiving output signals outputted by said data detecting circuits and for outputting a write completion signal when all the output signals indicate that data are written properly in said memory cells in which data are to be written.

2. A memory system, comprising:

a first memory, said first memory including a plurality of electrically erasable and programmable memory cells, said memory cells capable of being arranged in units of page and in units of block, wherein each unit of page includes at least two memory cells, and wherein each unit of block includes at least two pages, and wherein a common line is provided for each memory cell in a corresponding block so as to provide an erasure of said each memory cell in the corresponding block when an erase voltage is provided on the common line, said first memory further including a plurality of data latch circuits for programming the memory cells in a corresponding page, each data latch circuit storing data of one of a first and a second logic level, said each data latch circuit being initially set to initial data corresponding to one of the first and second logic levels based on externally-input data;

a program termination detector connected to the first memory and configured to detect whether or not all of the data latch circuits are storing data at the second logic level, the program termination detector outputting a verify signal when detecting that said all of the data latch circuits are storing data at the second logic level;

a second memory connected to the first memory and configured to temporarily store the initial data to be input into the first memory; and

a control circuit connected to the first memory, the second memory, and the program termination detector, said control circuit configured to program the first memory on a page-by-page based by inputting the initial data stored in the second memory into the first memory for programming a first page of the first memory, and when the control circuit receives the verify signal output from the program termination detector indicating that the programming of the first page has been completed, the control circuit inputs the initial data stored in the second memory into the first memory for programming a second page of the first memory.

3. The memory system according to claim 2, wherein the second memory is a SRAM.

4. The memory system according to claim 2, wherein the first memory has a NAND-type cell structure.

5. The memory system according to claim 2, wherein the common line for each block is connected to a substrate on which the memory cells of said each block are formed.

6. The memory system according to claim 2, wherein the memory cells form a memory cell array of rows and columns, and

wherein a first page and a second page of the memory device belong to a same row.

7. The memory system according to claim 2, wherein the program termination detector simultaneously determines whether or not each data latch circuit stores the second logic level.

8. The memory system according to claim 2, wherein the second memory is capable of storing the initial data of at least one block.

9. The memory system according to claim 2, wherein the memory system further comprises a third memory configured in a same manner as the first memory, and

wherein the second memory is capable of storing the initial data of at least two blocks.

10. The memory system according to claim 2, wherein the second memory is capable of storing the initial data of at least three blocks.

11. The memory system according to claim 2, wherein the memory system further comprises a data bus, and

wherein the initial data are transferred from the second memory to the first memory through the data bus.

12. The memory system according to claim 2, wherein the second memory stores the initial data of at least two pages.

13. The memory system according to claim 2, wherein the data of the first logic level stored in the data latch circuits corresponding to the memory cells which have been successfully programmed are modified to the second logic level.