Multiplexing process in an asynchronous transfer mode telecommunication network and switching node implementing the process

• US 5,793,766 A
• Filed: 06/18/1996
• Issued: 08/11/1998
• Est. Priority Date: 06/19/1995
• Status: Expired due to Term

• Current Assignee: Alcatel-Lucent France, SA (Nokia Corporation)
• Original Assignee: Alcatel-Lucent France, SA (Nokia Corporation)
• Inventors: Glon, Jean-Pierre, Dieudonne, Marc
• Primary Examiner(s): Nguyen, Chau
• Application Number:
  US08/664,615
• Time in Patent Office: 784 Days
• Field of Search: 370/395, 370/465, 370/466, 370/468, 370/397, 370/470, 370/471, 370/474, 370/522, 370/472, 370/528, 370/473, 370/477, 370/537, 370/538
• US Class Current: 370/395.1
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04Q 11/0478 Provisions for broadband connections

Abstract

A multiplexing process in an asynchronous transfer mode telecommunication network consists in placing a payload in a series of cells supporting the same logical channel a series of data containers supporting the same logical channel, each container including a load that is a quantity of data greater than the payload of each cell. In one preferred embodiment the payload of each container is composite. It includes conventional synchronous digital channel samples and data micropackets each of which has a label indicating a logical channel and the length of the packet. Applications include ATM telecommunication networks.

Claims

1. A multiplexing process, in an asynchronous transfer mode telecommunication network, for time-division multiplexing data in asynchronous transfer mode cells of fixed length, each cell including:

a header containing a virtual circuit group identifier and a virtual circuit identifier that define a logical channel between two nodes of said network; and

a payload made up of a fixed quantity of data;

said process comprising the steps of;

before routing data in one of said nodes, placing a payload in each of a series of cells supporting a same logical channel, wherein a series of logical entities, referred to as data containers, support the same logical channel, each container including a load that is a quantity of data greater than that of the payload of each cell; and

choosing a quantity of data conveyed by each container so that the use of said one node is more efficient; and

to send data to different destinations, placing a plurality of data packets in the series of containers supporting the same logical channel;

each of said plurality of data packets including a label containing a logical reference and indicating the length of the packet.

2. The multiplexing process according to claim 1, further comprising the step of, to further send samples of a plurality of signals from different circuits to different destinations, placing samples in a series of containers supporting a given logical channel,

said samples respectively corresponding to said circuits, and each sample being identifiable within a container by its position in said container.

3. Process according to claim 1 wherein the position of all the samples from a given circuit is fixed for the entire duration of said circuit.

4. Process according to claim 2 wherein the position of the samples from a given circuit is variable for the duration of said circuit and sample position change protocol primitives are conveyed in containers.

5. Process according to claim 1 wherein the start of each container is identified by a predetermined flag.

6. Process according to claim 1 wherein the length of said containers transmitted over a given link is able to vary and container length change protocol primitives are transmitted in the payload of a container before any change of length is effected.

7. A switching node for implementing a multiplexing process, in an asynchronous transfer mode telecommunication network, for time-division multiplexing data in asynchronous transfer mode cells of fixed length, each cell including:

a header containing a virtual circuit group identifier and a virtual circuit identifier that define a logical channel between two nodes of said network; and

a payload made up of a fixed quantity of data;

said process comprising the steps of;

before routing data in one of said nodes, placing a payload in each of a series of cells supporting a same logical channel, wherein a series of logical entities, referred to as data containers, supports the same logical channel, each container including a load that is a quantity of data greater than that of the payload of each cell; and

choosing a quantity of data conveyed by each container so that the use of said one node is more efficient; and

to send data to different destinations, placing a plurality of data packets in the series of containers supporting the same logical channel, each packet including a label containing a logical reference and indicating the length of the packet;

said switching node comprising;

a first stage including at least one first auxiliary switching matrix for grouping into the same container, data received by said node and contained in different cells, said received data being routed over the same path during at least part of their routing in said node, each container being conveyed by the series of cells supporting the same logical channel and conveying the quantity of data greater than that of the payload of each cell;

at least one conventional intermediate cell switching stage having inputs coupled to outputs of said first stage;

a final stage including at least one second auxiliary switching matrix for placing, in separate cells respectively supporting separate logical channels, data that has been conveyed in the same cell because it had been grouped in the same container; and

each said auxiliary switching matrix comprising;

a first marker memory dedicated to routing data packets; and

a first space switch controlled by routing data stored in said first marker memory to place data packets in a cell.

8. The switching node according to claim 7, wherein at least one auxiliary switching matrix further comprises:

a second marker memory dedicated to routing synchronous circuit samples; and

a second space switch controlled by data stored in said first marker memory to place synchronous circuit samples in a cell.

9. The switching node according to claim 8, further comprising:

for optimizing resources within a container to be sent, means for assigning each circuit sample a position in said container, modifying the content of the second marker memory accordingly and placing circuit sample position change protocol primitives in said container for all the circuits set up; and

means for, on receipt of a container, interpreting primitives conveyed by said container and indicating position changes, to determine the positions of the samples conveyed in said container, and updating accordingly said second marker memory.

10. A switching node for implementing a multiplexing process, in an asynchronous transfer mode telecommunication network, for time-division multiplexing data in asynchronous transfer mode cells of fixed length, each cell including:

a header containing a virtual circuit group identifier and a virtual circuit identifier that define a logical channel between two nodes of said network; and

a payload made up of a fixed quantity of data;

said process comprising the steps of;

before routing data in one of said nodes, placing a payload in each of a series of cells supporting a same logical channel, wherein a series of logical entities, referred to as data containers, supports the same logical channel, each container including a load that is a quantity of data greater than that of the payload of each cell; and

choosing a quantity of data conveyed by each container so that the use of said one node is more efficient; and

to send samples of a plurality of signals from different circuits and to send data to different destinations, placing the following items in the series of containers supporting the same logical channel, each container having a fixed length;

samples respectively corresponding to said circuits, each sample being identifiable within a container by its position in said container; and

a plurality of data packets each including a label indicating its length and its destination;

said switching node comprising;

a main cell switching network having main inputs, constituting the inputs of said node, and main outputs constituting the outputs of said node; and

at least one auxiliary cell switching network having inputs, respectively connected to auxiliary outputs of said main network, and outputs respectively connected to auxiliary inputs of said main network, in order to;

group in the same container, having a capacity greater than the payload of a cell, data contained in different cells, said data being routable over the same path for at least part of its routing in said node, and each container being conveyed by the series of cells supporting the same logical channel; and

place in separate cells, supporting respective different logical channels, data conveyed in the same cell because it was grouped in the same container; and

said at least one auxiliary switching matrix comprising;

a first marker memory dedicated to routing data packets; and

a first space switch controlled in accordance with routing data stored in said second marker memory to place data packets in a cell.

11. The switching node according to claim 10, wherein at least one auxiliary switching matrix further comprises:

a second marker memory dedicated to routing synchronous circuit samples; and

a second space switch controlled in accordance with data stored in the first marker memory to place synchronous circuit samples in a cell.

12. The switching node according to claim 11, further comprising:

for optimizing resources within a container to be sent, means for assigning each circuit sample a position in said container, modifying the content of the second marker memory accordingly and placing circuit sample position change protocol primitives in said container for all the circuits set up; and

means for, on receipt of a container, interpreting primitives conveyed by said container and indicating position changes, to determine the positions of the samples conveyed in said container, and updating accordingly said second marker memory.

13. A switching node for implementing a multiplexing process, in an asynchronous transfer mode telecommunication network, for time-division multiplexing data in asynchronous transfer mode cells of fixed length, each cell including:

a header containing a virtual circuit group identifier and a virtual circuit identifier that define a logical channel between two nodes of said network; and

a payload made up of a fixed quantity of data;

said process comprising the steps of;

before routing data in one of said nodes, placing a payload in each of a series of cells supporting a same logical channel, wherein a series of logical entities, referred to as data containers, supports the same logical channel, each container including a load that is a quantity of data greater than that of the payload of each cell; and

choosing a quantity of data conveyed by each container so that the use of said one node is more efficient; and

to send samples of a plurality of signals from different circuits and to send data to different destinations, placing the following items in the series of containers supporting the same logical channel, each container having a fixed length;

samples respectively corresponding to said circuits, each sample being identifiable within a container by its position in said container; and

a plurality of data packets each including a label indicating its length and its destination;

said switching node comprising;

a first stage including at least one first auxiliary switching matrix for grouping into the same container, data received by said node and contained in different cells, said received data being routed over the same path during at least part of their routing in said node, each container being conveyed by the series of cells supporting the same logical channel and conveying the quantity of data greater than that of the payload of each cell;

at least one conventional intermediate cell switching stage having inputs coupled to outputs of said first stage;

a final stage including at least one second auxiliary switching matrix for placing, in separate cells respectively supporting separate logical channels, data that has been conveyed in the same cell because it had been grouped in the same container; and

each said auxiliary switching matrix comprising;

a first marker memory dedicated to routing synchronous circuit samples;

a first space switch controlled by data stored in said first marker memory to place synchronous circuit samples in a cell;

a second marker memory dedicated to routing data packets; and

a second space switch controlled by routing data stored in said first marker memory to place data packets in a cell.

14. The switching node according to claim 13, further comprising:

for optimizing resources within a container to be sent, means for assigning each circuit sample a position in said container, modifying the content of the first marker memory accordingly and placing circuit sample position change protocol primitives in said container for all the circuits set up, and

means for, on receipt of a container, interpreting primitives conveyed by said container and indicating position changes, to determine the positions of the samples conveyed in said container, and updating accordingly said first marker memory.

15. A switching node for implementing a multiplexing process, in an asynchronous transfer mode telecommunication network, for time-division multiplexing data in asynchronous transfer mode cells of fixed length, each cell including:

a header containing a virtual circuit group identifier and a virtual circuit identifier that define a logical channel between two nodes of said network; and

a payload made up of a fixed quantity of data;

said process comprising the steps of;

before routing data in one of said nodes, placing a payload in each of a series of cells supporting a same logical channel, wherein a series of logical entities, referred to as data containers, supports the same logical channel, each container including a load that is a quantity of data greater than that of the payload of each cell; and

choosing a quantity of data conveyed by each container so that the use of said one node is more efficient; and

to send samples of a plurality of signals from different circuits and to send data to different destinations, placing the following items in the series of containers supporting the same logical channel, each container having a fixed length;

samples respectively corresponding to said circuits, each sample being identifiable within a container by its position in said container; and

a plurality of data packets each including a label indicating its length and its destination;

said switching node comprising;

a main cell switching network having main inputs, constituting the inputs of said node, and main outputs constituting the outputs of said node; and

at least one auxiliary cell switching network having inputs, respectively connected to auxiliary outputs of said main network, and outputs respectively connected to auxiliary inputs of said main network, in order to;

group in the same container, having a capacity greater than the payload of a cell, data contained in different cells, said data being routable over the same path for at least part of its routing in said node, and each container being conveyed by the series of cells supporting the same logical channel; and

place in separate cells, supporting respective different logical channels, data conveyed in the same cell because it was grouped in the same container; and

said at least one auxiliary switching matrix comprising;

a first marker memory dedicated to routing synchronous circuit samples;

a first space switch controlled in accordance with data stored in the first marker memory to place synchronous circuit samples in a cell;

a second marker memory dedicated to routing data packets; and

a second space switch controlled in accordance with routing data stored in said second marker memory to place data packets in a cell.