Structure and method for SDRAM dynamic self refresh entry and exit using JTAG

• US 5,793,776 A
• Filed: 10/18/1996
• Issued: 08/11/1998
• Est. Priority Date: 10/18/1996
• Status: Expired due to Term

• Current Assignee: Samsung Electronics Co. Ltd.
• Original Assignee: Samsung Electronics Co. Ltd.
• Inventors: Qureshi, Amjad, Baeg, Sanghyeon
• Primary Examiner(s): Beausoliel, Jr., Robert W.
• Assistant Examiner(s): Iqbal, Nadeem
• Application Number:
  US08/733,817
• Time in Patent Office: 662 Days
• Field of Search: 371/22.1, 371/21.1, 371/22.31, 371/22.32, 371/22.5, 371/42, 365/201, 365/222, 365/189.01, 365/233, 395/881, 395/285, 395/183.06, 395/183.18, 324/765
• US Class Current: 714/724
• CPC Class Codes: G11C 29/32 Serial access; Scan testing

Abstract

JTAG test logic and a memory controller place an SDRAM in a self refresh mode prior to beginning JTAG testing. The memory controller can complete a current memory access and otherwise prepare for the JTAG test. During the JTAG test, self refresh mode operation of the SDRAM retains data without the need for a clock signal or refresh signals which are suspended for the JTAG test. Accordingly, after the JTAG test, circuit operation can continue without reinitializing data in the SDRAM.

Claims

1. A circuit test method comprising:

asserting a first signal to a memory controller unit from a test logic circuit to indicate a start of the circuit test;

asserting a second signal from said memory controller unit to said test logic circuit to indicate that said memory controller unit has finished the current memory access;

placing of a dynamic memory coupled to said memory controller unit into a self refresh mode in response to both said first signal and said second signal being asserted; and

testing a circuit while said dynamic memory is in said self refresh mode, said self-refresh mode being used to preserve pretest contents of said dynamic memory during said testing.

2. The method of claim 1, wherein testing disables a clock signal used by said dynamic memory when in an operating mode.

3. The method of claim 1 wherein testing stops a refresh signal to said dynamic memory.

4. The method of claim 1, further comprising asserting a third signal from said test logic circuit to a system clock generator block, said third signal causing a bypass of said system clock generator block.

5. The method of claim 4, further comprising:

asserting a fourth signal to said memory controller unit from said test logic circuit to indicate that said circuit test is complete; and

taking of said dynamic memory out of self refresh mode by said memory controller unit if said fourth signal is asserted.

16. The method of claim 1 wherein said circuit is a logic circuit.

6. A circuit comprising:

a memory controller;

a test logic coupled to said memory controller wherein prior to a circuit test, said test logic asserts a first signal that indicates to said memory controller that a system clock bypass is being requested and said memory controller asserts a second signal to said test logic when a current memory access operation is complete; and

a dynamic memory capable of operating in self refresh mode coupled to said memory controller, wherein said memory controller places said dynamic memory into said self refresh mode in response to said first signal and said second signal being asserted, said self refresh mode being used to preserve pretest contents of said dynamic memory during said circuit test.

7. The circuit of claim 6, further comprising a system clock generator block coupled to said test logic circuit, wherein said test logic circuit asserts a third signal prior to said circuit test to bypass said system clock generator block.

8. The circuit of claim 6, wherein said dynamic memory is an SDRAM.

9. The circuit of claim 6, wherein said test logic comprises:

a test controller; and

a set of shift registers coupled to both said memory controller and said test controller to allow for communication between said test controller and said memory controller.

10. The circuit of claim 9, wherein said test controller is a JTAG Controller.

11. The circuit of claim 9, wherein said set of shift registers comprise:

a Mode Control Register for holding instruction values; and

an Observation Control Register for holding status values.

12. The circuit of claim 11, wherein said Mode Control Register comprises a plurality of register cells through which data can be serially shifted without destroying the existing contents of each of said plurality of register cells.

13. The circuit of claim 11, wherein said Observation Control Register comprises a plurality of register cells through which data can be serially shifted without destroying the existing contents of each of said plurality of register cells.

14. The circuit of claim 6 wherein said circuit comprises an integrated circuit.

15. The circuit of claim 14 wherein said integrated circuit is a multimedia signal processor system.