Multiplex address/data bus with multiplex system controller and method therefor

• US 5,793,990 A
• Filed: 06/11/1993
• Issued: 08/11/1998
• Est. Priority Date: 06/11/1993
• Status: Expired due to Term

• Current Assignee: Future Link Systems, LLC (Vector Capital Corporation)
• Original Assignee: VLSI Technology, Inc. (Koninklijke Philips N.V.)
• Inventors: Jirgal, James J., Potts, Walter H., Evoy, David R.
• Primary Examiner(s): Sheikh, Ayaz R.
• Assistant Examiner(s): MYERS, PAUL R
• Application Number:
  US08/076,876
• Time in Patent Office: 1,887 Days
• Field of Search: 395/325, 395/281, 395/297, 395/304, 395/306, 395/307, 395/287
• US Class Current: 710/107
• CPC Class Codes: G06F 13/362 with centralised access control

Abstract

A computer system having a multiplex address/data bus with a multiplex system controller and method therefor is disclosed which provides in a computer system having time shared use of a multiplex address/data bus to reduce the number of required pins for devices within the computer system, a CPU having at least one address bus, at least one data bus, at least one memory input/output, and at least one CPU control bus coupled thereto for sending and receiving information. In addition, this system includes at least one memory input/output device coupled to a first portion of the address bus for sending and receiving at least one of address information and data information, at least one input/output only device coupled to a second portion of the address bus for sending and receiving at least one of address information and data information, and a multiplex system controller coupled to the CPU and the address bus and having a multiplex control bus coupled to both the memory input/output device and to the input/output only device for taking control of the address bus from the CPU.

Claims

1. In a computer system having timed shared use of buses to reduce the number of required pins for devices within said computer system, comprising, in combination:

Central Processing Unit (CPU) means having at least one address bus, at least one data bus, at least one memory input/output, and at least one CPU control bus coupled thereto for sending and receiving information;

at least one memory input/output means coupled to a first portion of said address bus for sending and receiving at least one of address information and data information;

at least one input/output only means coupled to a second portion of said address bus for sending and receiving at least one of address information and data information; and

multiplex system controller means coupled to said CPU means and to said address bus and having multiplex control bus means coupled to both said memory input/output means and to said input/output only means for time sharing said address bus of said CPU means in order to sequentially transfer groups of at least address and data information to said memory input/output means and said input/output only means comprising, in combination;

state machine means coupled to said multiplex control bus means and to said CPU control bus for controlling said multiplex system controller means;

address latch means coupled to said state machine means and to said address bus for temporarily storing address information; and

a plurality of multiplexer means each coupled to said address latch means, said data bus, said state machine means, and to a Direct Memory Access (DMA) controller for transferring data to said data bus and to said address bus in response to control signals from said state machine means.

2. The system of claim 1 wherein said state machine means is provided with priority signal means for interrupting a multiplex bus cycle.

3. The system of claim 1 wherein said multiplex system controller means is coupled to at least one Industry Standard Architecture (ISA) address bus and to at least one ISA data bus to provide multiplex bus cycle operation with ISA bus devices.

4. The system of claim 1 wherein said multiplex system controller means is coupled to said DMA controller to execute DMA cycles.

5. The system of claim 1 wherein said multiplex system controller means takes temporary control of said address bus from said CPU means to send a first group of bits comprising address bits, a second group of bits comprising address bits, and a third group of bits comprising data bits to said memory input/output means.

6. The system of claim 5 wherein said multiplex system controller means takes temporary control of said address bus from said CPU means to send a first group of bits comprising address bits, a second group of bits comprising address bits, and a third group of bits comprising data bits to said input/output only means.

7. The system of claim 6 wherein said first group of bits comprising address bits, said second group of bits comprising address bits, and said third group of bits comprising data bits each comprise 16 bits of information.

8. The system of claim 7 wherein a portion of said second group of bits comprising address bits selects at least a one byte address location for at least one corresponding byte of data.

9. In a computer system having timed shared use of buses to reduce the number of required pins for devices within said computer system, comprising, in combination:

CPU means located on a CPU bus controller chip having at least one CPU control bus, at least one address bus, and at least one data bus for sending and receiving information;

multiplex system controller means residing in said chip and coupled to each of said CPU control bus, said address bus, and said data bus for time sharing said address bus in order to sequentially transfer groups of at least address and data information and having multiplex control bus means coupled to both memory input/output means and input/output only means for taking control of said address bus comprising, in combination;

state machine means coupled to said multiplex control bus means and to said CPU control bus for controlling said multiplex system controller means;

address latch means coupled to said state machine means and to said address bus for temporarily storing address information; and

a plurality of multiplexer means each coupled to said address latch means, said data bus, and to said state machine means for transferring data to said data bus and to said address bus in response to control signals from said state machine;

CPU bus slave means coupling each of said CPU control bus, said address bus, and said data bus to said multiplex system controller means for coordinating data flow on each of said CPU control bus, said address bus, and said data bus;

at least one memory input/output means coupled to a first portion of said address bus for sending and receiving at least one of address and data information; and

at least one input/output only means coupled to a second portion of said address bus for sending and receiving at least one of address and data information.

10. The system of claim 9 wherein said CPU control bus provides memory input/output signals to both said memory input/output means and said input/output only means.

11. The system of claim 9 wherein said state machine means is provided with priority signal means for interrupting a multiplex bus cycle.

12. The system of claim 9 wherein said multiplex system controller means takes temporary control of said address bus from said CPU means to send a first group of bits comprising address bits, a second group of bits comprising address bits, and a third group of bits comprising data bits to said memory input/output means.

13. The system of claim 12 wherein said multiplex system controller means takes temporary control of said address bus from said CPU means to send a first group of bits comprising address bits, a second group of bits comprising address bits, and a third group of bits comprising data bits to said input/output only means.

14. The system of claim 13 wherein said first group of bits comprising address bits, said second group of bits comprising address bits, and said third group of bits comprising data bits each comprise 16 bits of information.

15. The system of claim 14 wherein a portion of said second group of bits comprising address bits selects at least a one byte address location for at least one corresponding byte of data.