Method for transmitting bus commands and data over two wires of a serial bus

• US 5,793,993 A
• Filed: 08/18/1995
• Issued: 08/11/1998
• Est. Priority Date: 08/18/1995
• Status: Expired due to Term

• Current Assignee: Intellectual Ventures I LLC (Intellectual Ventures LLC)
• Original Assignee: General Magic, Inc.
• Inventors: Watkins, John E., Perlman, Stephen G., Broedner, Walter F., Faddell, Anthony M.
• Primary Examiner(s): Ray, Gopal C.
• Application Number:
  US08/516,840
• Time in Patent Office: 1,089 Days
• Field of Search: 395/280, 395/182.02, 395/287, 395/309, 395/281, 395/200.2, 395/200.15, 395/182.03, 395/800, 395/750, 395/306, 395/200.13, 395/286, 340/825.06, 370/85.1, 370/85.2, 375/257
• US Class Current: 710/106
• CPC Class Codes: G06F 13/4291 using a clocked protocol

Abstract

A low power, single master, variable clock rate, daisy-chainable, serial bus connects a bus dispatch (master) to a chain of one or more daisy-chained peripheral devices (slaves). The bus has a bidirectional serial data line, a bidirectional clock line, unidirectional interrupt line, power and ground lines. All bus transactions over the bus occur under bus dispatch commands. If a peripheral device interrupts the bus dispatch, bus dispatch issues commands over the bus to determine which device caused the interrupt and what service is being requested by the device. The bus dispatch may then turn control of the data and clock lines over to the peripheral device for a limited amount of time depending on the service requested. New peripheral devices can be connected onto the bus and unused peripheral devices can be disconnected from the bus while the bus is operating without causing a bus failure. Similarly, bus dispatch may enter a low power sleep mode from which it may be awakened by a peripheral device. In some embodiments, additional lines such as battery charging lines and/or signal lines for other serial buses such as RS-232 and RS-422 are provided.

Claims

1. A method for transmitting bus commands and data over two wires of a serial bus comprising:

transmitting a bus command over said two wires by transmitting a command clock signal over a first wire of said two wires, and transmitting a bus command over a second wire of said two wires; and

transmitting data over said two wires by transmitting data over said first wire of said two wires and transmitting a data clock signal over said second wire of said two wires wherein only one of said bus command and data is transmitted over said two wires at a time.

2. A method for transmitting bus commands and data over a two-wire serial bus as in claim 1 wherein transmitting said bus command over said second wire of said two wires further comprises:

transmitting a plurality of bits of said bus command with a predetermined state.

3. A method for transmitting bus commands and data over a two-wire serial bus as in claim 2 wherein transmitting said plurality of bits of said bus command with a predetermined state further comprises:

transmitting first and second bits of said bus command with a predetermined state.

4. A method for transmitting bus commands and data over a two-wire serial bus as in claim 3 wherein said predetermined state comprises said first and second bits having a logic one level.

5. A method for transmitting bus commands and data over a two-wire serial bus as in claim 1 wherein transmitting said bus command over said second wire of said two wires further comprises:

transmitting a multi-byte bus command.

6. A method for transmitting bus commands and data over a two-wire serial bus as in claim 5 wherein transmitting said multi-byte bus command over said second wire of said two wires further comprises:

transmitting first and second bits of a first bus command byte with a predetermined state.

7. A method for transmitting bus commands and data over a two-wire serial bus as in claim 5 wherein transmitting said multi-byte bus command over said second wire of said two wires further comprises:

transmitting a plurality of address bits wherein said address bits identify a peripheral device that is to receive the bus command.

8. A method for transmitting bus commands and data over a two-wire serial bus as in claim 7 wherein transmitting said multi-byte bus command over said second wire of said two wires further comprises:

transmitting a microcontroller bit wherein upon said microcontroller bit having a predetermined state, a portion of said bus command is passed to a microcontroller in said peripheral device.

9. A method for transmitting bus commands and data over a two-wire serial bus as in claim 1 wherein transmitting said bus command over said second wire of said two wires further comprises:

transmitting a parity bit wherein said parity bit is set so that bits of the bus command have a predetermined parity.

10. A method for transmitting bus commands and data over a serial bus comprising:

transmitting bus commands and data over first and second wires of said serial bus wherein said transmitting bus commands and data further comprises;

transmitting a bus command by transmitting a command clock signal over said first wire, and transmitting said bus command over said second wire; and

transmitting data by transmitting data over said first wire, and transmitting a data clock signal over said second wire wherein only one of said bus command and data is transmitted over said first and second wires at a time; and

transmitting interrupt signals over a third wire of said serial bus.

11. A method for transmitting bus commands and data over a serial bus as in claim 10 further comprising:

supplying a bus power supply voltage over a fourth wire of said serial bus.

12. A method for transmitting bus commands and data over a serial bus as in claim 11 further comprising:

supplying a bus ground via a fifth wire of said serial bus.

13. A method for transmitting bus commands and data over a serial bus as in claim 11 further comprising:

buffering said bus commands, data and interrupt signals on said first, second, and third lines respectively in each peripheral device on said serial bus.

14. A method for transmitting bus commands and data over a serial bus as in claim 13 further comprising:

powering buffers used in said buffering step with said bus power supply voltage on said fourth wire.

15. A method for transmitting bus commands and data over a serial bus as in claim 10 wherein transmitting said bus command over said second wire further comprises:

transmitting a plurality of bits of said bus command with a predetermined state.

16. A method for transmitting bus commands and data over a serial bus as in claim 15 wherein transmitting said plurality of bits of said bus command with a predetermined state further comprises:

transmitting first and second bits of said bus command with said predetermined state.

17. A method for transmitting bus commands and data over a serial bus as in claim 16 wherein said predetermined state comprises said first and second bits having a logic one level.

18. A method for transmitting bus commands and data over a serial bus as in claim 10 wherein transmitting said bus command over said second wire further comprises:

transmitting a multi-byte bus command.

19. A method for transmitting bus commands and data over a serial bus as in claim 18 wherein transmitting said multi-byte bus command over said second wire further comprises:

transmitting first and second bits of a first command byte with a predetermined state.

20. A method for transmitting bus commands and data over a serial bus as in claim 18 wherein transmitting said multi-byte bus command over said second wire further comprises:

transmitting a plurality of address bits wherein said address bits identify a peripheral device that is to receive the bus command.

21. A method for transmitting bus commands and data over a serial bus as in claim 18 wherein transmitting said multi-byte bus command over said second wire further comprises:

transmitting a microcontroller bit wherein upon said microcontroller bit having a predetermined state, a portion of said bus command is passed to a microcontroller in a peripheral device.

22. A method for transmitting bus commands and data over a serial bus as in claim 10 wherein transmitting said bus command over said second wire further comprises:

transmitting a parity bit wherein said parity bit is set so that bits of the bus command have a predetermined parity.