Verification of strongly ordered memory accesses in a functional model of an out-of-order computer system

• US 5,794,012 A
• Filed: 10/09/1996
• Issued: 08/11/1998
• Est. Priority Date: 10/09/1996
• Status: Expired due to Term

• Current Assignee: Hewlett Packard Enterprise Development LP (Hewlett-Packard Enterprise Company)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Averill, Gregory S.
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): KAZIMI, HANI M
• Application Number:
  US08/728,338
• Time in Patent Office: 671 Days
• Field of Search: 395/500, 395/527, 395/672, 364/578, 364/264.3, 711/141, 711/147
• US Class Current: 703/21
• CPC Class Codes: G06F 11/261 by simulating additional hardware, e.g. fault simulation
• CPC Class Codes: G06F 11/28 by checking the correct order of processing G06F11/08 - G06F11/26 take precedence; monitoring patterns of pulse trains H03K5/19
• CPC Class Codes: G06F 30/33 Design verification, e.g. functional simulation or model checking

Abstract

A system and method for detecting architectural violations of strongly ordered instructions by a computer architecture under test that supports out-of-order instruction execution is presented. A synchronizer concurrently controls the execution of an architectural model, which models high-level architectural requirements of the computer architecture under test and generates correct results under all received instruction test stimuli, and a behavioral model, which models the high-level architectural requirements of the computer architecture under test and executes instruction test stimuli according to the out-f-order instruction execution behavior defined by the computer architecture. The synchronizer matches all out-of-order instruction execution effects. The synchronizer verifies the correct handling of strongly ordered instruction by the computer architecture under test by keeping track of coherency check addresses from the bus emulator to the behavioral model, each memory request issued by the behavioral model to the bus emulator for any memory address other than the coherency check address, each respective move-in of a copy of each memory address, each access of each of the logged memory addresses, and each access of each logged coherency check address. If between the issuance of a coherency check on a coherency check address and a subsequent access of the same coherency check address without a new move-in of the coherency check address, the behavioral model moves in a copy of a memory address and accesses that copy, an architectural violation in handling strongly ordered instructions by the computer architecture under test is indicated.

Claims

1. A system for detecting architectural violations of strongly ordered instructions in a computer architecture under test said computer architecture under test comprising a data cache and supporting out-of-order instruction execution, comprising:

an architectural model which models high-level architectural requirements of said computer architecture and generates correct results under all received instruction test stimuli;

a behavioral model which models said high-level architectural requirements of said computer architecture and executes said received instruction test stimuli according to out-of-order instruction execution behavior defined by said computer architecture;

a bus emulator which modest an external system environment;

a synchronizer which controls the execution of said architectrual model and said behavioral model, matches all out-of-order instruction execution effects, and, for each coherency check issued on a coherency check address to the bus emulator by said behavioral model, performs the steps of;

(i) creating a coherency check record corresponding to said coherency check address and recording said coherency check address in said coherency check record;

(ii) logging each memory request issued by said behavioral model to said bus emulator for any memory address other than said coherency check address;

(iii) logging each respective move-in of a copy of each memory address in step (ii);

(iv) logging each access by the instructions in the instruction stream of each memory address requested in step (ii);

(v) logging each access by the instructions in the instruction stream of said coherency check address; and

(vi) if between the issuance of said coherency check on said coherency check address in step (i) and a subsequent access of said coherency check address in step (v) without a new move-in of said coherency check address, said behavioral model moves in a copy of a memory address in step (iii) and accesses said copy, indicating an architectural violation by said behavioral model in handling strongly ordered instructions.

2. The computer-based test system of claim 1, wherein the external system environment comprises a plurality of processors which support out of order instruction execution.

3. A computer-based method for detecting architectural violations of strongly ordered instructions in an implementation or model of a computer architecture which has a data cache and supports out of order instruction execution, the implementation being modeled by a behavioral model, an external system environment being modeled by a bus emulator, and the computer architecture being modeled by an architectural model, the detection being performed by a synchronizer, the computer-based method comprising the steps of:

(1) executing said behavioral model in response to an instructions stream comprising a plurality of instructions, said behavioral model generating a behavioral model state in response to each instruction in said instruction stream, said bus emulator providing an external system environment state in response to each behavioral model state;

(2) executing said architectural model in response to the instruction stream;

(3) synchronizing the execution of the behavioral model with the execution of the architectural model such that the architectural model state and the behavioral model state are synchronous with the external system environment state;

(4) monitoring a coherency check command issued to the bus emulator by said behavioral model and detecting architectural violations of strongly ordered instructions by;

(i) logging a coherency check address;

(ii) maintaining a record of the coherency check address;

(iii logging each memory request of a memory address issued by the behavioral model to the bus emulator for any address other than the coherency check address;

(iv) logging the return of each memory request in step (iii);

(v) logging each access by the instructions in the instruction stream of each memory address requested in step (iii);

(vi) logging each access by the instructions in the instruction stream of the coherency check address; and

(vii) if between the issuance of said coherency check on said coherency check address and a subsequent access of said coherency check address in step (vi) without a new move-in of said coherency check address, said behavioral model moves in a copy of a memory address in step (iv) and accesses said copy in step (v), indicating an architectural violation by said behavioral model in handling strongly ordered instructions.

4. The computer-based method of claim 3, further comprising the steps of:

(5) halting execution of said architectural model and said behavioural model when said synchronizer indicates an architectural violation by said behavioral model in handling strongly ordered instructions.