Architectural support for execution control of prologue and eplogue periods of loops in a VLIW processor
First Claim
1. An apparatus comprising:
- a prologue distinguishing register complex responsive to physical iterations of loop body code, wherein the state of the prologue distinguishing register complex advances toward an end of prologue state in correspondence with the physical iterations of the loop body code;
an epilogue distinguishing register responsive to the physical iterations of the loop body code, wherein the state of the epilogue distinguishing register advances toward a beginning of epilogue state in correspondence with the physical iterations of the loop body code;
side-effects enabling logic coupled to the prologue distinguishing register complex and responsive to the state thereof, wherein the side-effects enabling logic supplies a side-effects enabled predicate except during a prologue period of the loop body; and
loads enabling logic coupled to the epilogue distinguishing register and responsive to the state thereof, wherein the loads enabling logic supplies a loads enabled predicate except during an epilogue period of the loop body.
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Accused Products
Abstract
For certain classes of software pipelined loops, prologue and epilogue control is provided by loop control structures, rather than by predicated execution features of a VLIW architecture. For loops compatible with two simple constraints, code elements are not required for disabling garbage operations during prologue and epilogue loop periods. As a result, resources associated with implementation of the powerful architectural feature of predicated execution need not be squandered to service loop control. In particular, neither increased instruction width nor an increased number of instructions in the loop body is necessary to provide loop control in accordance with the present invention. Fewer service functions are required in the body of a loop. As a result, loop body code can be more efficiently scheduled by a compiler and, in some cases, fewer instructions will be required, resulting in improved loop performance. Loop control logic includes a loop control registers having an epilogue counter field, a shift register, a side-effects enabled flag, a current loop counter field, a loop mode flag, and side-effects manual control and loads manual control flags. Side-effects enabling logic and load enabling logic respectively issue a side-effects enabled predicate and a loads enabled predicate to respective subsets of execution units. Software pipelined simple and inner loops are supported.
47 Citations
19 Claims
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1. An apparatus comprising:
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a prologue distinguishing register complex responsive to physical iterations of loop body code, wherein the state of the prologue distinguishing register complex advances toward an end of prologue state in correspondence with the physical iterations of the loop body code; an epilogue distinguishing register responsive to the physical iterations of the loop body code, wherein the state of the epilogue distinguishing register advances toward a beginning of epilogue state in correspondence with the physical iterations of the loop body code; side-effects enabling logic coupled to the prologue distinguishing register complex and responsive to the state thereof, wherein the side-effects enabling logic supplies a side-effects enabled predicate except during a prologue period of the loop body; and loads enabling logic coupled to the epilogue distinguishing register and responsive to the state thereof, wherein the loads enabling logic supplies a loads enabled predicate except during an epilogue period of the loop body. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14)
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15. A method of controlling execution of software pipelined loop body code, the method comprising the steps of:
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initializing a prologue distinguishing register complex with an indication corresponding to a number of overlapped logical iterations minus one (NOVL-1) in the loop body code; initializing an epilogue distinguishing register with an indication corresponding to a number of logical iterations in the loop body code; advancing the state of the prologue distinguishing register complex toward an end of prologue state in correspondence with physical iterations of the loop body code; advancing the state of the epilogue distinguishing register toward a beginning of epilogue state in correspondence with physical iterations of the loop body code; after the prologue distinguishing register complex reaches the end of prologue state, supplying a side-effects enabled predicate to a first execution unit providing execution support for operations of the loop body code that cause side-effects; and until the epilogue distinguishing register reaches the beginning of epilogue state, supplying a loads enabled predicate to a second execution unit providing execution support for load operations of the loop body code. - View Dependent Claims (16, 17, 18)
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19. A method for providing a computer system apparatus, the method comprising the steps of:
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providing a prologue distinguishing register complex responsive to physical iterations of loop body code, wherein the state of the prologue distinguishing register complex advances toward an end of prologue state in correspondence with the physical iterations of the loop body code; providing an epilogue distinguishing register responsive to the physical iterations of the loop body code, wherein the state of the epilogue distinguishing register advances toward a beginning of epilogue state in correspondence with the physical iterations of the loop body code; providing side-effects enabling logic coupled to the prologue distinguishing register complex and responsive to the state thereof, wherein the side-effects enabling logic supplies a side-effects enabled predicate except during a prologue period of the loop body; and providing loads enabling logic coupled to the epilogue distinguishing register and responsive to the state thereof, wherein the loads enabling logic supplies a loads enabled predicate except during an epilogue period of the loop body.
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Specification