System and method for dynamically reconfigurable computing using a processing unit having changeable internal hardware organization

• US 5,794,062 A
• Filed: 04/17/1995
• Issued: 08/11/1998
• Est. Priority Date: 04/17/1995
• Status: Expired due to Fees

• Current Assignee: Ricoh Corporation (Ricoh Company Limited)
• Original Assignee: Ricoh Company Limited, Ricoh Corporation (Ricoh Company Limited)
• Inventors: Baxter, Michael A.
• Primary Examiner(s): AN, MENG AI T
• Application Number:
  US08/423,560
• Time in Patent Office: 1,212 Days
• Field of Search: 395/800, 395/301, 395/489, 395/578, 395/800.29, 395/800.15, 395/800.3, 395/800.28, 395/307, 395/284, 395/311, 395/312, 395/200.5, 395/200.53 , 395/200.54, 395/800.2, 395/376, 364/DIG. 2
• US Class Current: 712/30
• CPC Class Codes: G06F 15/7867 with reconfigurable architecture
• CPC Class Codes: G06F 8/447 Target code generation
• CPC Class Codes: G06F 8/47 Retargetable compilers
• CPC Class Codes: G06F 9/06 using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
• CPC Class Codes: G06F 9/30043 LOAD or STORE instructions; Clear instruction
• CPC Class Codes: G06F 9/30101 Special purpose registers
• CPC Class Codes: G06F 9/30134 Register stacks; shift registers
• CPC Class Codes: G06F 9/30167 of immediate specifier, e.g. constants
• CPC Class Codes: G06F 9/30174 for non-native instruction set, e.g. Javabyte, legacy code
• CPC Class Codes: G06F 9/30181 Instruction operation extension or modification
• CPC Class Codes: G06F 9/3822 Parallel decoding, e.g. parallel decode units
• CPC Class Codes: G06F 9/3824 Operand accessing
• CPC Class Codes: G06F 9/3828 with global bypass, e.g. between pipelines, between clusters
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units
• CPC Class Codes: G06F 9/3897 with adaptable data path
• CPC Class Codes: G06F 9/44521 Dynamic linking or loading; Link editing at or after load time, e.g. Java class loading

Abstract

A set of S-machines, a T-machine corresponding to each S-machine, a General Purpose Interconnect Matrix (GPIM), a set of I/O T-machines, a set of I/O devices, and a master time-base unit form a system for scalable, parallel, dynamically reconfigurable computing. Each S-machine is a dynamically reconfigurable computer having a memory, a first local time-base unit, and a Dynamically Reconfigurable Processing Unit (DRPU). The DRPU is implemented using a reprogrammable logic device configured as an Instruction Fetch Unit (IFU), a Data Operate Unit (DOU), and an Address Operate Unit (AOU), each of which are selectively reconfigured during program execution in response to a reconfiguration interrupt or the selection of a reconfiguration directive embedded within a set of program instructions. Each reconfiguration interrupt and each reconfiguration directive references a configuration data set specifying a DRPU hardware organization optimized for the implementation of a particular Instruction Set Architecture (ISA). The IFU directs reconfiguration operations, instruction fetch and decode operations, memory access operations, and issues control signals to the DOU and the AOU to facilitate instruction execution. The DOU performs data computations, and the AOU performs address computations. Each T-machine is a data transfer device having a common interface and control unit, one or more interconnect I/O units, and a second local time-base unit. The GPIM is a scalable interconnect network that facilitates parallel communication between T-machines. The set of T-machines and the GPIM facilitate parallel communication between S-machines.

Claims

1. A dynamically reconfigurable processing unit for executing program instructions to process data, the dynamically reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set, the dynamically reconfigurable processing unit when configured as the first hardware architecture being responsive to a reconfigure directive to change the internal hardware organization of the dynamically reconfigurable processing unit to be configured as the second hardware architecture;

wherein the changeable internal hardware organization of the dynamically reconfigurable processing unit comprises an instruction fetch unit having a data input, a first control output, and a second control output, for sequencing instruction execution operations within the dynamically reconfigurable processing unit, the data input coupled to a data port of a memory.

2. The dynamically reconfigurable processing unit of claim 1, wherein the instruction fetch unit further comprises:

an architecture description memory having an output, the architecture description memory storing a set of architecture description signals including an interrupt response signal that specifies a manner in which the dynamically reconfigurable processing unit responds to an interrupt signal when configured to implement an instruction set architecture;

an instruction state sequencer having an input and an output, for controlling an instruction execution cycle and transition between an instruction fetch state, an instruction decode state, an instruction execution state, and a write-back state; and

an interrupt state machine having an input and an output, for generating a transition control signal that specifies a state within the instruction execution cycle for which a transition to an interrupt service state is allowed, the input of the interrupt state machine coupled to the output of the architecture description memory, the output of the interrupt state machine coupled to the input of the instruction state sequencer.

3. A dynamically reconfigurable processing unit for executing program instructions to process data, the dynamically reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set, the dynamically reconfigurable processing unit when configured as the first hardware architecture being responsive to a reconfigure directive to change the internal hardware organization of the dynamically reconfigurable processing unit to be configured as the second hardware architecture;

wherein the changeable internal hardware organization of the dynamically reconfigurable processing unit comprises a data operate unit having a data port and a control input, for performing operations upon data, the data port of the data operate unit coupled to the data port of the memory and the control input coupled to receive control signals;

and wherein the data operate unit comprises;

a switch having a data port, a control input, a feedback input, and an output, for selectively routing data between said data port, said feedback input, and said output, said data port of the switch coupled to the data port of the memory, said control input of the switch coupled to receive control signals;

a store/align unit having an input, an output, and a control input, for storing data, the input of the store/align unit coupled to the output of the switch, the control input of the store/align unit coupled to receive control signals; and

a data operate circuit having an input, an output, and a control input, for performing data computations, the input of the data operate circuit coupled to the output of the store/align unit, the output of the data operate unit coupled to the feedback input of the switch, and the control input of the data operate logic coupled to receive control signals.

4. The dynamically reconfigurable processing unit of claim 3, wherein the store/align unit is reconfigurable and can be selectively configured as one selected from the group consisting of a random-access memory and a pipelined register in response to control signals for a corresponding instruction set architecture.

5. The dynamically reconfigurable processing unit of claim 3, wherein the data operate unit is reconfigurable and can be selectively configured as one selected from the group consisting of an arithmetic-logic unit and a pipelined functional unit according to signals in response to control signals for a corresponding instruction set architecture.

6. A dynamically reconfigurable processing unit for executing program instructions to process data, the dynamically reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set, the dynamically reconfigurable processing unit when configured as the first hardware architecture being responsive to a reconfigure directive to change the internal hardware organization of the dynamically reconfigurable processing unit to be configured as the second hardware architecture;

wherein the changeable internal hardware organization of the reconfigurable processing unit comprises an address operate unit having a control input, an address input, and an output, for performing operations upon addresses, the address input coupled to a data port of a memory, and the output of the address operate unit coupled to an address input of the memory, and the control input of the address operate unit coupled to receive control signals;

and wherein the address operate unit comprises;

a switch having a data port, a control input, a feedback input, and an output, for selectively routing addresses between said data port, said feedback input, and said output in response to control signal receive on said control input, said data port of the switch coupled to the data port of the memory;

a store/count unit having an input, an output, and a control input, for storing data, the input of the store/count unit coupled to the output of the switch, the control input of the store/count logic coupled to receive control signals; and

an address operate circuit having an input, an output, and a control input, for performing address computations, the input of the address operate circuit coupled to the output of the store/count unit, the output of the address operate circuit coupled to the feedback input of the switch, and the control input of the address operate unit coupled to receive control signals.

7. The dynamically reconfigurable processing unit of claim 6, wherein the store/count unit is reconfigurable and can be selectively configured as one selected from the group consisting of a Random Access Memory and a register in response to signals received on the control input of the store/count unit.

8. A system for dynamically reconfigurable computing comprising:

a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set; and

a first communication device having an input, and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;

the first communication device further having a first data port and a second data port, the system further comprising;

a second reconfigurable processing unit for executing program instructions to process data, the second reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions;

a second communication device having an input, an output, a first data port, and a second data port, for transferring data to and from the second reconfigurable processing unit, the input of the second communication device coupled to the output of the second reconfigurable processing unit, and the output of the second communication device coupled to the input of the second reconfigurable processing unit; and

an interconnect means for routing data and having a plurality of communication channels, the first data port of the first communication device, the second data port of the first communication device, the first data port of the second communication device, and the second data port of the second communication device each coupled to one of the plurality of communication channels.

9. The system of claim 8 wherein the first reconfigurable processing unit is dynamically reconfigurable independent from reconfiguration of the second reconfigurable processing unit.

10. The system of claim 8 further comprising:

a third reconfigurable processing unit for executing program instructions to process data, the third reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions; and

a third communication device having an input, an output, a first data port, and a second data port, for transferring data to and from the third reconfigurable processing unit, the input of the third communication device coupled to the output of the third reconfigurable processing unit, the output of the third communication device coupled to the input of the third reconfigurable processing unit, the first data port of the third communication device and the second data port of the third communication device each coupled to one of the plurality of communication channels of the interconnect means.

11. A system for dynamically reconfigurable computing comprising:

a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set; and

a first communication device having an input, and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;

the first communication device further having a first data port and a second data port, the system further comprising;

a non-reconfigurable processing unit having a predefined architecture for executing a program of instructions formed from a single instruction set, the non-reconfigurable processing unit having an input, an output;

a second communication device having an input, an output, a first data port, and a second data port, for transferring data to and from the non-reconfigurable processing unit, the input of the second communication device coupled to the output of the non-reconfigurable processing unit, the output of the second communication device coupled to the input of the non-reconfigurable processing unit; and

an interconnect means for routing data and having a plurality of communication channels, the first data port of the first communication device, the second data port of the first communication device, the first data port of the second communication device, and the second data port of the second communication device each coupled to one of the plurality of communication channels.

12. A system for dynamically reconfigurable computing comprising:

a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set; and

a first communication device having an input, and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;

a second reconfigurable processing unit for executing program instructions to process data, the second reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions;

a second communication device having an input, an output, a first data port, and a second data port, for transferring data to and from the second reconfigurable processing unit, the input of the second communication device coupled to the output of the second reconfigurable processing unit, and the output of the second communication device coupled to the input of the second reconfigurable processing unit; and

an interconnect means for routing data and having a plurality of communication channels, the first data port of the first communication device, the second data port of the first communication device, the first data port of the second communication device, and the second data port of the second communication device each coupled to one of the plurality of communication channels.

13. A system for dynamically reconfigurable computing comprising:

a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set; and

a first communication device having an input, and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;

a memory storing a first configuration data set that corresponds to a first instruction set architecture for a serial instruction processor and a second configuration data set that corresponds to a second instruction set architecture for a parallel instruction processor, and wherein the first reconfigurable processing unit can be selectively configured as one from the group of a serial instruction processor and a parallel instruction processor in response to signals from the memory, the first reconfigurable processing unit being coupled to the memory;

wherein the first reconfigurable processing unit is coupled to the memory by a plurality of signal lines and a first number of said plurality of signal lines forming address lines, a second number of said plurality of signal lines forming control lines and a third number of said plurality of signal lines forming data lines, the first number, second number and third number of said plurality of signal lines being reconfigurable and set according to a configuration data set utilized by the first reconfigurable processing unit.

14. The system of claim 13, wherein the instruction fetch unit comprises:

an architecture description memory having an output, the architecture description memory storing a set of architecture description signals including an interrupt response signal that specifies a manner in which the first reconfigurable processing unit responds to an interrupt signal when configured to implement an instruction set architecture;

an instruction state sequencer having an input and an output, for controlling an instruction execution cycle with an instruction fetch state, an instruction decode state, an instruction execution state, and a write-back state, the instruction execution cycle resulting in the execution of an instruction within the instruction set architecture; and

an interrupt state machine having an input and an output, for generating a transition control signal that specifies a state within the instruction execution cycle for which a transition to an interrupt service state is allowed, the input of the interrupt state machine coupled to the output of the architecture description memory, the output of the interrupt state machine coupled to the input of the instruction state sequencer.

15. A system for dynamically reconfigurable computing comprising:

a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set; and

a first communication device having an input, and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;

wherein the changeable internal hardware organization of the first reconfigurable processing unit comprises a reconfigurable data operate unit having a data port and a control input, for performing operations upon data, the data port of the data operate unit coupled to a data port of a memory and the control input coupled to receive control signals;

and wherein the reconfigurable data operate unit comprises;

a switch having a data port, a control input, a feedback input, and an output, for selectively routing data between said data port, said feedback input, and said output, said data port of the switch coupled to the data port of the memory, the control input of the switch coupled to the first control output of the instruction fetch unit;

a store/align unit having an input, an output, and a control input, for storing data and data computation results, the input of the store/align unit coupled to the output of the switch, the control input of the store/align unit coupled to the first control output of the instruction fetch unit; and

a data operate circuit having an input, an output, and a control input, for performing data computations, the input of the data operate circuit coupled to the output of the store/align unit, the output of the data operate circuit coupled to the feedback input of the switch, and the control input of the data operate circuit coupled to the first control output of the instruction fetch unit.

16. The system of claim 15, wherein the store/align unit is reconfigurable as one selected from the group consisting of a random-access memory and a pipelined register in response to control signals from the memory that are a configuration data set corresponding to a first instruction set architecture and a second instruction set architecture, respectively.

17. The system of claim 16, wherein the data operate unit is reconfigurable as one selected from the group consisting of an arithmetic-logic unit and a pipelined functional unit in response to configuration signals from the memory.

18. A system for dynamically reconfigurable computing comprising:

a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set; and

a first communication device having an input, and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;

wherein the changeable internal hardware organization of the first reconfigurable processing unit comprises a reconfigurable address operate unit having a control input, an address input, and an output, for performing operations upon addresses, the address input coupled to a data port of a memory, and the output of the address operate unit coupled to an address input of the memory, and the control input of the address operate unit coupled to receive control signals;

and wherein the reconfigurable address operate unit comprises;

a switch having a data port, a control input, a feedback input, and an output, for selectively routing addresses between said data port, said feedback input, and said output, said data port of the switch coupled to the data port of the memory, the control input of the switch coupled to the first control output of the instruction fetch unit;

a store/count unit having an input, an output, and a control input, for storing data, the input of the store/count unit coupled to the output of the switch, the control input of the store/count logic coupled to the second control output of the instruction fetch unit;

an address operate circuit having an input, an output, and a control input, for performing address computations, the input of the address operate circuit coupled to the output of the store/count unit, the output of the address operate circuit coupled to the feedback input of the switch, and the control input of the address operate unit coupled to the second control output of the instruction fetch unit.

19. The system of claim 18, wherein the store/count unit is reconfigurable and can be selectively configured as one from the group of a Random Access Memory and a register in response to signals received on the control input of the store/count unit.

20. The system of claim 18, wherein the address operate circuit is reconfigurable as one from the group of a register and a register and an arithmetic unit in response to signals received on the control input of the address operate circuit.

21. A system for dynamically reconfigurable computing comprising:

a first reconfigurable processing unit for executing program instructions to process data, the first reconfigurable processing unit having an input, an output and a changeable internal hardware organization that is selectively changeable during execution of a sequence of program instructions between a first hardware architecture that executes instructions from a first instruction set and a second hardware architecture that executes instructions of a second instruction set; and

a first communication device having an input and an output, for transferring data to and from the first reconfigurable processing unit, the input of the first communication device coupled to the output of the first reconfigurable processing unit, and the output of the first communication device coupled to the input of the first reconfigurable processing unit;

wherein the first reconfigurable processing unit comprises;

a reconfigurable instruction fetch unit having a data input, a first control output, and a second control output, for sequencing instruction execution operations within the first reconfigurable processing unit, the data input coupled to a data port of a memory;

a reconfigurable data operate unit having a data port and a control input, for performing operations upon data, the data port of the data operate unit coupled to the data port of the memory and the control input coupled to the first control output of the instruction fetch unit; and

a reconfigurable address operate unit having a control input, an address input, and an output, for performing operations upon addresses, the control input of the address operate unit coupled to the second control output of the instruction fetch unit, the address input coupled to the data port of the memory, and the output of the address operate unit coupled to an address input of the memory.

22. The system of claim 21, wherein the reconfigurable instruction fetch unit, the reconfigurable data operate unit and the reconfigurable address operate unit can be reconfigurable during execution of an instruction by the first reconfigurable processing unit.