Apparatus and method for identifying the features and the origin of a computer microprocessor

• US 5,794,066 A
• Filed: 05/07/1996
• Issued: 08/11/1998
• Est. Priority Date: 08/31/1992
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Dreyer, Robert S., Lau, Daniel G., Pollack, Frederick J., Corwin, William M., Wang, Tsu-Hua
• Primary Examiner(s): Bowler, Alyssa H.
• Assistant Examiner(s): Davis, Jr., Walter D.
• Application Number:
  US08/644,678
• Time in Patent Office: 826 Days
• Field of Search: 395/800, 395/500, 395/427, 395/800.32, 395/800.42, 395/568, 711/100
• US Class Current: 712/32
• CPC Class Codes: G06F 11/006 Identification G06F11/2289 takes precedence
• CPC Class Codes: G06F 21/73 by creating or determining hardware identification, e.g. serial numbers
• CPC Class Codes: G06F 2207/7219 Countermeasures against side channel or fault attacks
• CPC Class Codes: G06F 9/30003 Arrangements for executing specific machine instructions
• CPC Class Codes: G06F 9/328 for runtime instruction patching
• CPC Class Codes: G06F 9/44505 Configuring for program initiating, e.g. using registry, configuration files

Abstract

A multi-level identification apparatus and method for providing at least two types of identification information, including a first type for identifying the origin of a microprocessor and the number of levels of identification information available, and a second type for identifying a family, a model, a stepping ID, and features of a microprocessor. The apparatus includes a first memory element for storing an indicia string that identifies the origin of the microprocessor. The apparatus also includes a second memory element for storing other microprocessor ID data including data fields for specifically identifying the microprocessor. The apparatus includes control logic for executing an ID instruction that reads the indicia string or the microprocessor ID data, dependent upon a preselected type. Whichever identification information is read, it is stored in one or more general purpose registers for selective reading by a programmer. The method is available at any time while the microprocessor is operating.

Claims

1. A method for determining microprocessor attributes in response to an ID instruction, wherein the microprocessor performs the steps comprising:

a) reading a first type of information from a processor memory element in the microprocessor in response to the ID instruction, wherein the first type of information specifies an available number of levels of identification information;

b) storing at least a portion of the first type of information in at least one register in the microprocessor;

c) retrieving additional information from the processor memory element, if the first type of information indicates that more than one level of information is available.

2. The method of claim 1 wherein the additional information comprises data fields of microprocessor-specific information including at least one of a family data field, a revision history data field, a serial number data field, and a model data field.

3. A method of identifying a microprocessor in response to an ID instruction from a program executing on the microprocessor, wherein the microprocessor performs the steps comprising:

a) receiving the ID instruction;

b) receiving a level indicator identifying a level of microprocessor identification information from a plurality of levels of microprocessor identification information stored in a memory in the microprocessor;

c) reading a selected microprocessor identification information from the memory in accordance with the level indicator; and

d) storing at least a portion of the selected microprocessor identification information in a microprocessor memory register for access by the program.

4. The method of claim 3 wherein the selected microprocessor identification information includes feature data indicative of features of the microprocessor.

5. The method of claim 3 wherein the selected microprocessor identification information includes an indicia of origin of the microprocessor.

6. A method for determining microprocessor attributes in response to an ID instruction, wherein the microprocessor performs the steps comprising:

a) reading a first type of microprocessor identification information from a processor memory element in the microprocessor in response to the ID instruction, the processor memory element storing levels of microprocessor identification information;

b) storing at least a portion of the first type of information in at least one register in the microprocessor;

c) comparing the first type of information with a predetermined string;

d) retrieving additional microprocessor identification information from the processor memory element, if the first type of information matches the predetermined string.

7. The method of claim 6 wherein the first type of microprocessor identification information is an indicia of origin.

8. The method of 7 wherein the indicia of origin includes a string of consecutive characters, the consecutive characters comprising "INTEL".

9. The method of 8 wherein the consecutive characters are stored in a reverse order as "LETNI".

10. In a microprocessor, an identification apparatus for identifying the microprocessor in response to an ID instruction, the apparatus comprising:

a register;

a processor memory element storing multiple levels of microprocessor identification information;

a decoder for decoding program instructions including an ID instruction associated with a level indicator operand; and

control circuitry coupled to the decoder, said control circuitry reading at least one level of microprocessor identification information from the processor memory element in accordance with the level indicator operand and storing at least a portion of the one level of microprocessor identification information in the register in response to the ID instruction received by the decoder.

11. The apparatus of claim 10 wherein the processor memory element is a read only memory.

12. The apparatus of claim 10 wherein the control circuitry includes microcode.

13. The apparatus of claim 10 wherein the levels of microprocessor identification data includes feature data representing features of the microprocessor.

14. The apparatus of claim 10 wherein the at least one level of microprocessor identification data includes a consecutive string of characters, wherein the characters include "INTEL".

15. The apparatus of claim 14 wherein the consecutive string of characters is stored in reverse order as "LETNI".