Digital signal processing device

• US 5,794,067 A
• Filed: 09/29/1995
• Issued: 08/11/1998
• Est. Priority Date: 10/03/1994
• Status: Expired due to Fees

• Current Assignee: Ricoh Company Limited
• Original Assignee: Ricoh Company Limited
• Inventors: Kadowaki, Yukio
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US08/536,134
• Time in Patent Office: 1,047 Days
• Field of Search: 395/800, 395/800.34, 395/800.35
• US Class Current: 712/35
• CPC Class Codes: G06F 15/7857 using interleaved memory addressing G06F12/0607
• CPC Class Codes: G06F 9/30145 Instruction analysis, e.g. decoding, instruction word fields
• CPC Class Codes: G06F 9/3885 using a plurality of independent parallel functional units

Abstract

A digital signal processing device includes: a processing unit which performs basic operations, the processing unit transmitting an instruction signal including an instruction described by an instruction code when a special-function operation is performed; a plurality of functional blocks, each connected to the processing unit, which perform special-function operations in accordance with the instruction signal; a bus which interconnects the processing unit and the respective functional blocks to transmit a data signal and the instruction signal; and a block selecting unit, responsive to a status signal, which transmits an enable signal to at least one of the functional blocks to select the above-mentioned at least one of the functional blocks, so that the selected functional block is enabled to receive the instruction signal via the bus and to perform at least one of the special-function operations in accordance with the instruction signal, thereby generating processed data which is transmitted back to the processing unit.

Claims

1. A digital signal processing device comprising:

processing means for performing basic operations including multiplication, addition, data transfer and sequence control operations and for transmitting an instruction signal and a data signal, whereby said instruction signal includes an instruction code, when predetermined special-function operations different from said basic operations are to be performed;

a plurality of functional block means for performing said predetermined specialfunction operations in accordance with the instruction code of said instruction signal outputted by said processing means and for generating and outputting processed data to said processing means;

bus means for carrying the instruction signal and the data signal outputted by the processing means to at least one of said plurality of functional block means and for carrying the processed data of at least one of said plurality of functional block means to the processing means; and

block selecting means, connected between said plurality of functional block means and said processing means, responsive to a status signal, for selecting at least one of said plurality of functional block means and for transmitting an enable signal to at least one of said plurality of functional block means enabling said at least one of said plurality of functional block means to receive the instruction signal and the data signal outputted by the processing means via said bus means and to perform at least one of the predetermined special-function operations in accordance with the instruction code of the instruction signal.

2. The digital signal processing device according to claim 1, wherein said block selecting means receives either the status signal transmitted by said processing means or an external status signal transmitted by an external unit, said block selecting means selecting at least one of said functional block means in accordance with either the status signal or the external status signal.

3. The digital signal processing device according to claim 1, wherein, when the instruction signal is transmitted by said processing means, the instruction indicated by said instruction signal includes a functional-block control instruction contained in an instruction area of the instruction and a basic-operation control instruction contained in another instruction area of the instruction.

4. The digital signal processing device according to claim 1, wherein, when the instruction signal is transmitted by said processing means to one of said functional block means, the instruction indicated by said instruction signal includes a functional-block control instruction contained in an instruction area of the instruction,

wherein said one of said functional block means is enabled by said instruction signal to perform a special-function operation in accordance with said functional-block control instruction.

5. The digital signal processing device according to claim 1, wherein, when the instruction signal is transmitted by said processing means to two or more of said functional block means, the instruction indicated by said instruction signal includes a functional-block control instruction contained in an instruction area of the instruction,

wherein said functional-block control instruction is shared by said two or more of said functional block means to perform two or more specialfunction operations of different kinds.

6. The digital signal processing device according to claim 1, wherein said plurality of functional block means are included in a programmable logic device, and at least one functional block means in said programmable logic device is selected by said block selecting means in accordance with a determination of the status signal which is made in a program.

7. The digital signal processing device according to claim 1, wherein each of said functional block means has an input for inputting the enable signal transmitted by said block selecting means.

8. The digital signal processing device according to claim 1, wherein each of said functional block means includes a data register which retains data pieces supplied from the processing means and an instruction register which retains the instruction transmitted by the processing means.

9. A digital signal processing device comprising:

a processing unit for performing basic operations including multiplication, addition, data transfer and sequence control operations and for transmitting an instruction signal and a data signal, whereby said instruction signal includes an instruction code, when predetermined special-function operations different from said basic operations are to be performed;

a plurality of functional block units for performing said predetermined specialfunction operations in accordance with the instruction code of said instruction signal outputted by said processing unit and for generating and outputting processed data to said processing unit;

a bus for carrying the instruction signal and the data signal outputted by the processing unit to at least one of said plurality of functional block units and for carrying the processed data of at least one of said plurality of functional block units to the processing unit; and

a block selecting unit, connected between said plurality of functional block units and said processing unit responsive to a status signal, for selecting at least one of said plurality of functional block units and for transmitting an enable signal to at least one of said plurality of functional block units enabling said at least one of said plurality of functional block units to receive the instruction signal and the data signal outputted by the processing unit via said bus and to perform at least one of the predetermined special-function operations in accordance with the instruction code of the instruction signal.