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Low cost, highly parallel memory tester

  • US 5,794,175 A
  • Filed: 09/09/1997
  • Issued: 08/11/1998
  • Est. Priority Date: 09/09/1997
  • Status: Expired due to Term
First Claim
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1. Automatic test equipment for semiconductor devices comprising:

  • a) an array having a plurality of sockets for memory devices under test;

    b) pattern generator circuitry having a plurality of data lines, a plurality of address lines, a strobe line and an output enable line extending therefrom;

    c) fanout circuitry comprising;

    i) a plurality of latches, each having a data input connected to a portion of the plurality of sockets for memory devices under test and a clock input;

    ii) a plurality of buffer amplifiers connecting the address and data lines to each of the plurality of sockets for memory devices under test;

    iii) a programmable delay circuit connecting the strobe signal to the clock inputs of the plurality of latches, the programmable delay circuit having a control input;

    iv) routing circuitry having an input connected to the output enable line and a plurality of outputs, each connected to a portion of the plurality of sockets for memory devices under test, the routing circuitry also having a control input;

    v) wherein the control input of the programmable delay circuit is coupled to the control input of the routing circuit.

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