Low cost, highly parallel memory tester
First Claim
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1. Automatic test equipment for semiconductor devices comprising:
- a) an array having a plurality of sockets for memory devices under test;
b) pattern generator circuitry having a plurality of data lines, a plurality of address lines, a strobe line and an output enable line extending therefrom;
c) fanout circuitry comprising;
i) a plurality of latches, each having a data input connected to a portion of the plurality of sockets for memory devices under test and a clock input;
ii) a plurality of buffer amplifiers connecting the address and data lines to each of the plurality of sockets for memory devices under test;
iii) a programmable delay circuit connecting the strobe signal to the clock inputs of the plurality of latches, the programmable delay circuit having a control input;
iv) routing circuitry having an input connected to the output enable line and a plurality of outputs, each connected to a portion of the plurality of sockets for memory devices under test, the routing circuitry also having a control input;
v) wherein the control input of the programmable delay circuit is coupled to the control input of the routing circuit.
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Abstract
Automatic test equipment for semiconductor memories that provides testing of large arrays of semiconductor memory chips in parallel. Such massively parallel memory testing greatly enhances test throughput, thereby reducing cost. It greatly enhances the economics of testing memory device made according to a RAMBUS standard, which includes a low speed port and a medium speed port because it allows the same automatic test equipment to economically be used to test devices with the low speed port and the medium speed port.
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Citations
17 Claims
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1. Automatic test equipment for semiconductor devices comprising:
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a) an array having a plurality of sockets for memory devices under test; b) pattern generator circuitry having a plurality of data lines, a plurality of address lines, a strobe line and an output enable line extending therefrom; c) fanout circuitry comprising; i) a plurality of latches, each having a data input connected to a portion of the plurality of sockets for memory devices under test and a clock input; ii) a plurality of buffer amplifiers connecting the address and data lines to each of the plurality of sockets for memory devices under test; iii) a programmable delay circuit connecting the strobe signal to the clock inputs of the plurality of latches, the programmable delay circuit having a control input; iv) routing circuitry having an input connected to the output enable line and a plurality of outputs, each connected to a portion of the plurality of sockets for memory devices under test, the routing circuitry also having a control input; v) wherein the control input of the programmable delay circuit is coupled to the control input of the routing circuit. - View Dependent Claims (2, 3, 4, 5, 6, 7)
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8. Automatic test equipment for semiconductor devices comprising:
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a) an array having a plurality of sockets for memory devices under test; b) pattern generator circuitry having a plurality of data lines, a plurality of address lines, a strobe line and an output enable line extending therefrom; c) fanout circuitry comprising; i) a plurality of latches, each having a data input connected to a portion of the plurality of sockets for memory devices under test and a latch input, causing the latch to store the data at its input when the latch input is asserted; ii) at least one buffer amplifier, connecting the address and data lines to each of the plurality of sockets for memory devices under test; iii) routing circuitry having an input connected to the output enable line and a plurality of outputs, each connected to a portion of the plurality of sockets for memory devices under test, the routing circuitry also having a control input; iv) wherein the control input of the programmable delay circuit is coupled to the control input of the routing circuit; d) a programmable delay circuit coupling the strobe signal to the latch inputs of the plurality of latches, the programmable delay circuit having a control input, with the control input to the programmable delay circuit being coupled to the control input of the routing circuit. - View Dependent Claims (9, 10)
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11. A method of operating automatic test equipment for semiconductor devices, comprising the steps of:
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a) loading a plurality of semiconductor memory devices into an array of test sites; b) providing address and data signals to each of the semiconductor memory devices to store data into each of the semiconductor memory devices contemporaneously; c) providing address signals to each of the semiconductor memory devices and selectively providing an output enable signal to portions of the plurality of semiconductor memory devices; d) latching the data read from the memories with a strobe signal that has been delayed in proportion to the physical location of the portion of the plurality of memory devices that received an output enable signal; and e) processing the latched data to detect defects in the semiconductor memory devices. - View Dependent Claims (12, 13, 14, 15, 16, 17)
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Specification