Simple repair method for phase shifting masks

• US 5,795,685 A
• Filed: 01/14/1997
• Issued: 08/18/1998
• Est. Priority Date: 01/14/1997
• Status: Expired due to Fees

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Neisser, Mark O., Liebmann, Lars W., Lin, Burn Jeng
• Primary Examiner(s): Rosasco, S.
• Application Number:
  US08/783,631
• Time in Patent Office: 581 Days
• Field of Search: 430/5, 364/490, 395/500, 356/390
• US Class Current: 430/5
• CPC Class Codes: G03F 1/26 Phase shift masks [PSM]; PSM blanks; Preparation thereof
• CPC Class Codes: G03F 1/70 Adapting basic layout or design of masks to lithographic process requirements, e.g., second iteration correction of mask patterns for imaging
• CPC Class Codes: G03F 1/72 Repair or correction of mask defects

Abstract

A method and apparatus for correcting defects in a phase shift mask to be used in photolithography. More specifically, the method of the invention includes creating a second repair mask which contains phase shifters. Regions surrounding the defects on the first mask are made opaque. The design circuitry located in these defective regions is copied onto the second mask. During a second exposure the design circuitry is placed onto the semiconductor wafer. Therefore, this method and apparatus provides an inexpensive solution to a difficult problem.

Claims

1. A method of correcting a plurality of defects in an image enhancing mask, comprising the steps of:

a) locating the plurality of defects;

b) defining a plurality of repair regions;

c) making the plurality of repair regions opaque on the image enhancing mask; and

d) defining a pattern on an image enhancing repair mask to complement the plurality of repair regions.

2. The method of claim 1 wherein the image enhancing mask comprises phase shift openings and non-phase shift openings.

3. The method of claim 1 wherein said plurality of defects are located using AIMs.

4. The method of claim 1 wherein said plurality of repair regions are defined using a CAD/CAM system.

5. The method of claim 1 wherein the image enhancing mask performs a trimming function.

6. The method of claim 1 wherein the image enhancing repair mask performs a repair function, a trimming function, and a design function.

7. The method of claim 1 wherein the image enhancing repair mask performs a design function.

8. The method of claim 1 wherein said plurality of repair regions terminate in noncritical regions.

9. The method of claim 1 wherein said plurality of repair regions include circuitry.

10. The method of claim 1 wherein the plurality of defects comprise misplaced chrome and phase shift errors.

11. A method of correcting a plurality of defects in a phase shifting mask used to expose an image on a semiconductor wafer comprising the following steps:

a) detecting the plurality of defects in a pattern of the phase shifting mask;

b) defining a plurality of repair regions surrounding each of said plurality of defects that need to be repaired;

c) making the plurality of repair regions opaque;

d) defining a pattern on a phase shift repair mask to complement the plurality of repair regions;

e) adjusting the pattern on the phase shift repair mask to align phase shifting edges;

f) exposing the phase shifting mask onto the semiconductor wafer; and

g) exposing the phase shifting repair mask onto the semiconductor wafer.

12. The method of claim 11, wherein a positive photoresist is used on the semiconductor wafer.

13. The method of claim 11, wherein a negative photoresist is used on the semiconductor wafer.

14. The method of claim 11, wherein each of said exposing steps is immediately followed by a development step.

15. The method of claim 11, wherein one development step follows all of said exposure steps.

16. A method of correcting a plurality of defects in a phase shift mask used to expose an image on a semiconductor wafer comprising the following steps:

a) detecting the plurality of defects in the phase shift mask;

b) defining a plurality of repair regions surrounding each of said plurality of defects that need to be repaired;

c) making the plurality of repair regions opaque;

d) defining a pattern on a phase shift repair mask to complement the plurality of repair regions;

e) adjusting the phase shift repair mask;

f) exposing the phase shift repair mask onto the semiconductor wafer; and

g) exposing the phase shift mask onto the semiconductor wafer.

17. The method of claim 16, wherein each said exposing step is immediately followed by a development step.

18. The method of claim 16, wherein all of the exposing steps are completed before a development step.

19. A method of correcting a plurality of defects in a phase shifting mask used to expose an image on a semiconductor wafer comprising the following steps:

a) detecting the plurality of defects in the phase shifting mask;

b) defining a plurality of repair regions surrounding each of said plurality of defects that need to be repaired;

c) making the plurality of repair regions opaque;

d) defining a pattern on a phase shift repair mask to complement the plurality of repair regions;

e) adjusting the phase shift repair mask;

f) defining the area on the phase shift repair mask that needs to be trimmed;

g) defining a pattern on the trim mask to complement the trim area;

h) exposing the phase shift mask onto the semiconductor wafer;

i) exposing the phase shift repair mask onto the semiconductor wafer; and

j) exposing the trim mask onto the semiconductor wafer.

20. The method of claim 19 wherein each said exposing step is immediately followed by a development step.

21. The method of claim 19 wherein a development step follows the completion of all the said exposing steps.

22. A phase shift mask system comprising:

a phase shift mask including a plurality of phase shift openings, a plurality of non-phase shift openings, and a plurality of defects; and

a phase shift repair mask including a plurality of repair areas which operatively cooperate with the plurality of defects in the phase shift mask.

23. The phase shift mask system of claim 22 wherein the phase shift openings are alternating phase shifting openings.

24. The phase shift mask system of claim 22 wherein the phase shift openings are rim phase shifting openings.

25. The phase shift mask system of claim 22 wherein the phase shift openings are subresolution phase shifting openings.

26. The phase shift mask system of claim 22 wherein the phase shift openings are phase edge shifting openings.

27. The phase shift mask system of claim 22 wherein the phase shift openings are attenuated phase shifting openings.

28. The phase shift mask system of claim 22 wherein the phase shift openings are unattenuated phase shifting openings.

29. The phase shift mask system of claim 22 wherein the phase shift mask and the phase shift repair mask each include subresolution imaging with unattenuated phase shift openings.

30. The phase shift mask of claim 22, wherein the phase shift openings are chromeless phase shifting openings.

31. The phase shift mask of claim 22, wherein the phase shifting openings are Levenson phase shifting openings.

32. The phase shift mask of claim 22, wherein the phase shifting openings include outrigger phase shifting openings.

33. The phase shift mask system of claim 22, wherein the phase shift openings are used selectively depending on the critical image contrast requirement.

34. The phase shift repair mask of claim 22, wherein said phase shifting repair mask comprises phase shifters and intensity mask elements.

35. The phase shift mask system of claim 22, wherein the plurality of repairing areas include circuitry.

36. The phase shift mask system of claim 22, wherein the phase shift repair mask includes trim areas and second design areas.

37. A phase shift mask system comprising:

a phase shift mask including a plurality of phase shift openings, a plurality of non-phase shift openings, and a plurality of defects;

a phase shifting repair mask including a plurality of repair areas which operatively cooperate with the plurality of defects in the phase shifting mask; and

a trim mask which operatively cooperates with the phase shifting repair mask.

38. A method of collecting a plurality of defects, comprising the steps of:

a) locating the plurality of defects;

b) defining a plurality of repair regions;

c) making the plurality of repair regions opaque on a mask which includes an image enhancing mask section and a image enhancing repair mask section; and

d) defining a pattern on the image enhancing repair mask section to complement the plurality of repair regions.

39. The method of claim 38, wherein the image enhancing mask section and the image enhancing repair mask section are located on one mask.

40. A method of correcting a plurality of defects comprising the following steps:

a) detecting the plurality of defects in a pattern of a phase shift mask section;

b) defining a plurality of repair regions surrounding each of said plurality of defects that need to be repaired;

c) making the plurality of repair regions opaque;

d) defining a pattern on a phase shift repair mask section to complement the plurality of repair regions;

e) adjusting the pattern on the phase shift repair mask section to align phase shifting edges;

f) exposing the phase shift mask section onto the semiconductor wafer; and

g) exposing the phase shift repair mask section onto the semiconductor wafer.

41. The method of claim 40, wherein the phase shift mask section and phase shift repair mask section are located on one mask.

42. A method of correcting a plurality of defects comprising the following steps:

a) detecting the plurality of defects in a phase shift mask section;

b) defining a plurality of repair regions surrounding each of said plurality of defects that need to be repaired;

c) making the plurality of repair regions opaque;

d) defining a pattern on a phase shift repair mask section to complement the plurality of repair regions;

e) adjusting the phase shift repair mask section;

f) exposing the phase shift repair mask section onto the semiconductor wafer; and

g) exposing the phase shift mask section onto the semiconductor wafer.

43. The method of claim 42, wherein the phase shift mask section and the phase shift repair mask section are located on one mask.

44. A method of correcting a plurality of defects comprising the following steps:

a) detecting the plurality of defects in a phase shift mask section;

b) defining a plurality of repair regions surrounding each of said plurality of defects that need to be repaired;

c) making the plurality of repair regions opaque;

d) defining a pattern on a phase shift repair mask section to complement the plurality of repair regions;

e) adjusting the phase shift repair mask section;

f) defining the area on the phase shift repair mask section that needs to be trimmed;

g) defining a pattern on a trim mask section to complement a trim area;

h) exposing the phase shift mask section onto the semiconductor wafer;

i) exposing the phase shift repair mask section onto the semiconductor wafer; and

j) exposing the trim mask section onto the semiconductor wafer.

45. The method of claim 44, wherein the phase shift mask section, the phase shift repair section, and the trim mask section are located on one mask.

46. A phase shift mask system comprising:

a phase shift mask section including a plurality of phase shift openings, a plurality of non-phase shift openings, and a plurality of defects; and

a phase shift repair mask section including a plurality of repair areas which operatively cooperate with the plurality of defects in the phase shift mask.

47. The phase shift mask system of claim 46, wherein the phase shift mask section and the phase shift mask repair section are located on one mask.