Method of making memory chips using memory tester providing fast repair

• US 5,795,797 A
• Filed: 08/18/1995
• Issued: 08/18/1998
• Est. Priority Date: 08/18/1995
• Status: Expired due to Term

• Current Assignee: Teradyne Incorporated
• Original Assignee: Teradyne Incorporated
• Inventors: Chester, Michael A., Michaelson, Steven A.
• Primary Examiner(s): DUTTON, BRIAN KEITH
• Application Number:
  US08/516,709
• Time in Patent Office: 1,096 Days
• Field of Search: 437/8, 365/200, 371/10.3, 438/4
• US Class Current: 438/4
• CPC Class Codes: G11C 29/72 with optimized replacement algorithms

Abstract

A process for manufacturing semiconductor memories which includes a method of quickly and effectively identifying which faulty memory cells are to be replaced by redundant memory structures. Redundant rows and columns are assigned to replace rows and columns with faulty cells in an iterative process. At each pass, one row or column is identified for replacement. A row or column is selected for replacement based on priorities assigned to the faulty cells within the rows and columns. The highest priority cell for a row is the one in a column with the fewest other faulty cells. Where multiple cells have the same highest row priority, the cell in a row with the most faulty cells is given a higher priority. A similar dual measure is used for assigning column priorities to cells. Once a highest priority row and column are identified, the single element with the highest priority is identified. In cases where multiple structures have the same highest priority, alternative criteria are used to select a single element for replacement. Preprocessing is used to focus, at each iteration, on the best faulty elements to replace. One preprocessing technique is to constrain the choice for replacement to faulty cells within certain clusters, which, based on the distribution of failures will require either a row or column for repair. Another preprocessing technique is to constrain the choice for replacement to faulty cells within a segment which must use either a row or column for repair. When the choice for replacement in a group of faulty cells is constrained to faulty cells which require a redundant row or column for repair, only the priorities of the rows or columns, respectively, in that group of cells is considered.

Claims

1. A method of repairing a semiconductor memory having a plurality of memory structures including rows and columns of memory cells and redundant rows and columns, the method comprising:

a) testing the memory to identify faulty cells and creating in a computer a representation of the faulty cells;

b) assigning to selected ones of the faulty cells in the representation a first argument and a second argument, for each selected faulty cell the first argument representing the number of faulty cells in the same row and the second argument representing the number of faulty cells in the same column as said selected faulty cell, the arguments having values that can be ordered from high to low;

c) assigning priorities to said faulty cells in the representation based

i) primarily on one of either the first or second arguments, with lower valued arguments being assigned a higher priority; and

ii) secondarily on the other of the first or second arguments, with larger valued arguments being assigned a higher priority;

d) using the assigned priorities to select a faulty cell from the faulty cells to which priorities were assigned at step c);

e) allocating a redundant memory structure to repair the faulty cell selected at step d), the redundant memory structure being a row when the argument used in the step of primarily prioritizing represents said number of faulty cells in the same column as the faulty cell selected at step d) and the redundant memory structure being a column when the argument used in the step of primarily prioritizing represents the number of faulty cells in the same row as the faulty cell selected at step d).

2. The method of claim 1 additionally comprising the steps of

a) altering the representation of the faulty cells to remove faulty cells replaced by the allocated redundant memory structure;

b) repeating steps b) through e) of claim 1.

3. The method of claim 2 wherein steps a) and b) of claim 2 are repeated until no faulty cells remain in the representation or all redundant rows and columns are allocated.

4. The method of claim 2 wherein the step of allocating comprises constructing in a computer memory a data structure indicating which memory structure of the semiconductor memory being repaired are to be replaced by redundant memory structures.

5. The method of making a semiconductor memory using the method of claim 4, and additionally comprising the steps of:

a) providing the data structure to a repair station; and

b) physically altering the semiconductor memory in accordance with the replacement information in the data structure.

6. The method of claim 1 wherein the steps of claim 1 are repeated for each region of the semiconductor memory.

7. The method of claim 1 wherein the step of assigning arguments to selected faulty cells comprises:

a) identifying clusters of mutually, exclusively collinear faulty cells; and

b) selecting at least one cluster and assigning values to faulty cells within the selected cluster.

8. The method of claim 7:

a) additionally comprising the step of assigning to each cluster logic values indicating whether the cluster can be repaired using only unallocated redundant rows or repaired using only unallocated redundant columns; and

b) wherein the step of selecting a cluster comprises, when any of the clusters has a logic value indicating it can not be repaired with either only unallocated redundant rows or only unallocated redundant columns, selecting at least one such cluster.

9. The method of claim 1 wherein the semiconductor memory is organized into at least one region with each region having a plurality of segments, each segment containing memory structures, and each segment having associated with it redundant memory structures, with the redundant memory structures associated with each segment being associated with at least one other segment in the region:

a) additionally comprising the step of assigning to each segment logic values indicating whether the segment can be repaired using only unallocated redundant rows or repaired using only unallocated redundant columns;

b) wherein the step of selecting a faulty cell comprises the step of, when at least one of the segments has a logic value indicating it can not be repaired with either only unallocated redundant rows or only unallocated redundant columns, selecting a faulty cell in one of such segments.

10. In a process for manufacturing a semiconductor memory organized into rows and columns of memory cells, a method of replacing faulty memory cells with redundant rows and columns, the method comprising the steps of:

a) selecting a row or column to replace with a redundant element according to the steps of;

i) identifying clusters of faulty segments, each cluster containing mutually, exclusively co-linear cells,

ii) selecting as candidates for a column replacement those clusters which can not be repaired using only unallocated redundant rows;

iii) selecting as candidates for a row replacement those clusters which can not be repaired using only unallocated redundant columns;

iv) prioritizing the rows in each cluster selected as a candidate for row replacement and prioritizing the columns in each cluster selected as a candidate for column replacement; and

v) selecting a row or column with the highest priority;

b) allocating a redundant row or column to replace the selected row or column and repeating steps a) and b) until all rows and columns containing faulty cells have been selected for replacement at step a).

11. The method of manufacturing a semiconductor memory of claim 10 wherein

a) the memory is organized into segments, each segment having a unique combination of redundant rows and redundant columns which can be used to replace rows and columns in that segment;

and

b) the step of selecting a redundant row or column additionally comprises, when there are no clusters selected as candidates for row replacement or candidates for column replacement,

I) selecting as candidates for row replacement those segments having faulty cells which can not be repaired with only unallocated redundant columns;

ii) selecting as candidates for column replacement those segments having faulty cells which can not be repaired using unallocated redundant rows;

iii) prioritizing the rows in each segment selected as a candidate for row replacement and prioritizing the columns in each segment selected as a candidate for column replacement; and

iv) selecting a row or column with the highest priority.

12. The method of manufacturing a semiconductor memory of claim 10 wherein the step of prioritizing rows and columns comprises:

a) assigning a first value and a second value to each faulty cell within the row or column, which are

i) in the case of a row, the first being the number of faulty cells in the same column as the faulty cell and the second being the number of faulty cells in the same row as the faulty cell; and

ii) in the case of a column, the first being the number of faulty cells in the same row as the faulty cell and the second being the number of faulty cells in the same column as the faulty cell;

b) assigning a priority to the cells in each row and column, with the highest priority going to the cells with the lowest first value, and, when multiple cells have the same first value, the highest priority going to those with the highest second value,

c) using the priority of the highest priority cell in each row as the priority of that row and the highest priority cell in each column as the priority of that column.

13. The method of manufacturing a semiconductor memory of claim 12 wherein the step of selecting a row or column for replacement comprises separately selecting the highest priority row and the highest priority column and then selecting the row or column with the higher priority.

14. The method of manufacturing a semiconductor memory of claim 13 wherein the step of selecting the row or column with the higher priority comprises:

a) comparing the first value of the highest priority faulty cell in each row and column to select the row or column containing a cell with the lowest first value; and

b) when multiple rows or columns have highest priority cells having the same first value, selecting the row or column with the highest priority faulty cell having the highest second value.

15. The method of claim 14 wherein the step of selecting the row or column with the higher priority additionally comprises:

a) when multiple rows or columns have highest priority faulty cells having the same lowest first value and highest second value;

selecting the row or column which shares the fewest faulty cells with other rows or columns having highest priority faulty cells with the lowest first value and highest second value.

16. The method of claim 10 additionally comprising the steps, prior to the step of selecting a row or column to replace, of

a) determining which rows must be replaced because they contain more faulty cells than there are unallocated redundant columns and allocating a redundant row to those rows;

and

b) determining which columns must be replaced because they contain more faulty cells than there are unallocated redundant rows and allocating a redundant column to those columns.

17. A method of repairing a semiconductor memory having a plurality of rows and columns of cells, organized into segments, each segment having a unique combination of redundant rows and redundant columns, with certain of the cells in the memory being faulty, the method comprising the steps of:

a) selecting a row by;

i) for a first selected group of faulty cells, assigning a first value to each faulty cell representing the number of faulty cells in the same column and co-linear with the faulty cell and a second value representing the number of faulty cells in the same row and co-linear with the faulty cell;

ii) selecting the faulty cell with the lowest first value,

iii) when multiple faulty cells have the same first value, selecting the faulty cell that also has the highest second value;

iv) selecting the row containing the selected faulty cell

b) selecting a column by;

i) for a second selected group of faulty cells, assigning a first value to each faulty cell representing the number of faulty cells in the same row and co-linear with the faulty cell and a second value representing the number of faulty cells in the same column and co-linear with the faulty cell;

ii) selecting the faulty cell with the lowest first value,

iii) when multiple faulty cells have the same first value, selecting the faulty cell that also has the highest second value;

iv) selecting the column containing the selected faulty cell;

c) selecting from the selected row and the selected column the element having a faulty cell with the lowest first value and, when multiple elements contains faulty cell with the lowest first value, the highest second value.

18. The method of claim 17 wherein the first selected group of faulty cells and the second selected group of faulty cells are not identical.

19. The method of claim 18 wherein the first selected group of faulty cells comprises those faulty cells in one segment of the memory.

20. In a process of manufacturing a semiconductor memory having numerous cells organized into rows and columns with redundant elements organized as rows and columns, in which the redundant rows and columns are used to replace faulty cells within the memory, the method comprising the steps of:

a) segmenting at least a portion of the faulty cells into groups;

b) selecting as row groups those which contain more faulty cells in a row than there are unassigned redundant columns and selecting as column groups those which contain more faulty cells in a column than there are redundant row;

c) prioritizing the rows of faulty cells within the row groups and prioritizing the columns of faulty cells within the column groups to select the row or column with the highest priority; and

d) assigning a redundant element to the highest priority row or column; and

e) repeating steps a) through e) to assign another redundant element to faulty cells which are not included in a row a column to which a redundant element has been assigned.

21. The method of claim 20 wherein the groups of cells comprise clusters of faulty cells which are mutually and exclusively co-linear.

22. The method of claim 20 wherein the groups of cells comprise cells within a segment of the memory.

23. The method of claim 20 wherein the groups of cells comprise cells in clusters of faulty cells which are mutually and exclusively co-linear.

24. The method of claim 23 wherein the groups of cells are constrained to those cells in clusters which

a) have more faulty cells in a row then there are unassigned redundant columns or more faulty cells in a column than there are unassigned redundant rows, when there is at least one such cluster;

b) are in segments which have more faulty cells in a row then there are unassigned redundant columns or more faulty cells in a column than there are unassigned redundant rows, when there is at least one such segment.