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Method of making memory chips using memory tester providing fast repair

  • US 5,795,797 A
  • Filed: 08/18/1995
  • Issued: 08/18/1998
  • Est. Priority Date: 08/18/1995
  • Status: Expired due to Term
First Claim
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1. A method of repairing a semiconductor memory having a plurality of memory structures including rows and columns of memory cells and redundant rows and columns, the method comprising:

  • a) testing the memory to identify faulty cells and creating in a computer a representation of the faulty cells;

    b) assigning to selected ones of the faulty cells in the representation a first argument and a second argument, for each selected faulty cell the first argument representing the number of faulty cells in the same row and the second argument representing the number of faulty cells in the same column as said selected faulty cell, the arguments having values that can be ordered from high to low;

    c) assigning priorities to said faulty cells in the representation basedi) primarily on one of either the first or second arguments, with lower valued arguments being assigned a higher priority; and

    ii) secondarily on the other of the first or second arguments, with larger valued arguments being assigned a higher priority;

    d) using the assigned priorities to select a faulty cell from the faulty cells to which priorities were assigned at step c);

    e) allocating a redundant memory structure to repair the faulty cell selected at step d), the redundant memory structure being a row when the argument used in the step of primarily prioritizing represents said number of faulty cells in the same column as the faulty cell selected at step d) and the redundant memory structure being a column when the argument used in the step of primarily prioritizing represents the number of faulty cells in the same row as the faulty cell selected at step d).

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