Method of making memory chips using memory tester providing fast repair
First Claim
1. A method of repairing a semiconductor memory having a plurality of memory structures including rows and columns of memory cells and redundant rows and columns, the method comprising:
- a) testing the memory to identify faulty cells and creating in a computer a representation of the faulty cells;
b) assigning to selected ones of the faulty cells in the representation a first argument and a second argument, for each selected faulty cell the first argument representing the number of faulty cells in the same row and the second argument representing the number of faulty cells in the same column as said selected faulty cell, the arguments having values that can be ordered from high to low;
c) assigning priorities to said faulty cells in the representation basedi) primarily on one of either the first or second arguments, with lower valued arguments being assigned a higher priority; and
ii) secondarily on the other of the first or second arguments, with larger valued arguments being assigned a higher priority;
d) using the assigned priorities to select a faulty cell from the faulty cells to which priorities were assigned at step c);
e) allocating a redundant memory structure to repair the faulty cell selected at step d), the redundant memory structure being a row when the argument used in the step of primarily prioritizing represents said number of faulty cells in the same column as the faulty cell selected at step d) and the redundant memory structure being a column when the argument used in the step of primarily prioritizing represents the number of faulty cells in the same row as the faulty cell selected at step d).
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Accused Products
Abstract
A process for manufacturing semiconductor memories which includes a method of quickly and effectively identifying which faulty memory cells are to be replaced by redundant memory structures. Redundant rows and columns are assigned to replace rows and columns with faulty cells in an iterative process. At each pass, one row or column is identified for replacement. A row or column is selected for replacement based on priorities assigned to the faulty cells within the rows and columns. The highest priority cell for a row is the one in a column with the fewest other faulty cells. Where multiple cells have the same highest row priority, the cell in a row with the most faulty cells is given a higher priority. A similar dual measure is used for assigning column priorities to cells. Once a highest priority row and column are identified, the single element with the highest priority is identified. In cases where multiple structures have the same highest priority, alternative criteria are used to select a single element for replacement. Preprocessing is used to focus, at each iteration, on the best faulty elements to replace. One preprocessing technique is to constrain the choice for replacement to faulty cells within certain clusters, which, based on the distribution of failures will require either a row or column for repair. Another preprocessing technique is to constrain the choice for replacement to faulty cells within a segment which must use either a row or column for repair. When the choice for replacement in a group of faulty cells is constrained to faulty cells which require a redundant row or column for repair, only the priorities of the rows or columns, respectively, in that group of cells is considered.
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Citations
24 Claims
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1. A method of repairing a semiconductor memory having a plurality of memory structures including rows and columns of memory cells and redundant rows and columns, the method comprising:
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a) testing the memory to identify faulty cells and creating in a computer a representation of the faulty cells; b) assigning to selected ones of the faulty cells in the representation a first argument and a second argument, for each selected faulty cell the first argument representing the number of faulty cells in the same row and the second argument representing the number of faulty cells in the same column as said selected faulty cell, the arguments having values that can be ordered from high to low; c) assigning priorities to said faulty cells in the representation based i) primarily on one of either the first or second arguments, with lower valued arguments being assigned a higher priority; and ii) secondarily on the other of the first or second arguments, with larger valued arguments being assigned a higher priority; d) using the assigned priorities to select a faulty cell from the faulty cells to which priorities were assigned at step c); e) allocating a redundant memory structure to repair the faulty cell selected at step d), the redundant memory structure being a row when the argument used in the step of primarily prioritizing represents said number of faulty cells in the same column as the faulty cell selected at step d) and the redundant memory structure being a column when the argument used in the step of primarily prioritizing represents the number of faulty cells in the same row as the faulty cell selected at step d). - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9)
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10. In a process for manufacturing a semiconductor memory organized into rows and columns of memory cells, a method of replacing faulty memory cells with redundant rows and columns, the method comprising the steps of:
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a) selecting a row or column to replace with a redundant element according to the steps of; i) identifying clusters of faulty segments, each cluster containing mutually, exclusively co-linear cells, ii) selecting as candidates for a column replacement those clusters which can not be repaired using only unallocated redundant rows; iii) selecting as candidates for a row replacement those clusters which can not be repaired using only unallocated redundant columns; iv) prioritizing the rows in each cluster selected as a candidate for row replacement and prioritizing the columns in each cluster selected as a candidate for column replacement; and v) selecting a row or column with the highest priority; b) allocating a redundant row or column to replace the selected row or column and repeating steps a) and b) until all rows and columns containing faulty cells have been selected for replacement at step a). - View Dependent Claims (11, 12, 13, 14, 15, 16)
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17. A method of repairing a semiconductor memory having a plurality of rows and columns of cells, organized into segments, each segment having a unique combination of redundant rows and redundant columns, with certain of the cells in the memory being faulty, the method comprising the steps of:
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a) selecting a row by; i) for a first selected group of faulty cells, assigning a first value to each faulty cell representing the number of faulty cells in the same column and co-linear with the faulty cell and a second value representing the number of faulty cells in the same row and co-linear with the faulty cell; ii) selecting the faulty cell with the lowest first value, iii) when multiple faulty cells have the same first value, selecting the faulty cell that also has the highest second value; iv) selecting the row containing the selected faulty cell b) selecting a column by; i) for a second selected group of faulty cells, assigning a first value to each faulty cell representing the number of faulty cells in the same row and co-linear with the faulty cell and a second value representing the number of faulty cells in the same column and co-linear with the faulty cell; ii) selecting the faulty cell with the lowest first value, iii) when multiple faulty cells have the same first value, selecting the faulty cell that also has the highest second value; iv) selecting the column containing the selected faulty cell; c) selecting from the selected row and the selected column the element having a faulty cell with the lowest first value and, when multiple elements contains faulty cell with the lowest first value, the highest second value. - View Dependent Claims (18, 19)
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20. In a process of manufacturing a semiconductor memory having numerous cells organized into rows and columns with redundant elements organized as rows and columns, in which the redundant rows and columns are used to replace faulty cells within the memory, the method comprising the steps of:
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a) segmenting at least a portion of the faulty cells into groups; b) selecting as row groups those which contain more faulty cells in a row than there are unassigned redundant columns and selecting as column groups those which contain more faulty cells in a column than there are redundant row; c) prioritizing the rows of faulty cells within the row groups and prioritizing the columns of faulty cells within the column groups to select the row or column with the highest priority; and d) assigning a redundant element to the highest priority row or column; and e) repeating steps a) through e) to assign another redundant element to faulty cells which are not included in a row a column to which a redundant element has been assigned. - View Dependent Claims (21, 22, 23, 24)
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Specification