Semiconductor device having a plurality of circuits driven by different power sources and formed on the same substrate

• US 5,796,147 A
• Filed: 08/09/1994
• Issued: 08/18/1998
• Est. Priority Date: 08/09/1993
• Status: Expired due to Fees

• Current Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Original Assignee: Kabushiki Kaisha Toshiba (Toshiba Corporation)
• Inventors: Ono, Masayoshi
• Primary Examiner(s): Prenty, Mark V.
• Application Number:
  US08/288,188
• Time in Patent Office: 1,470 Days
• Field of Search: 257/368, 257/369, 257/355
• US Class Current: 257/355
• CPC Class Codes: H01L 27/0218 of field effect structures

Abstract

A semiconductor device has a semiconductor substrate including at least a first well and a second well which is electrically divided each other; a first electric circuit formed in the first well and connected to a first circuit power source through a source terminal; a second electric circuit formed in the second well and connected to a second circuit power source through a source terminal; a substrate ground well formed on the semiconductor substrate and connected to a third circuit power source which outputs a stable reference potential; a first protection diode connected between the source terminal of the first power source and the substrate ground well in the manner of being a reverse bias direction; and a second protection diode connected between the source terminal of the second power source and the substrate ground well in the manner of being a reverse direction.

Claims

1. A semiconductor device comprising:

a semiconductor substrate having at least a first well and a second well which are electrically divided from each other;

a first electric circuit formed in said first well and connected to a first circuit power source through a source terminal;

a second electric circuit formed in said second well and connected to a second circuit power source through a source terminal;

a substrate ground well formed on said semiconductor substrate and connected to a third circuit power source which outputs a stable reference potential;

a first protection diode connected between said source terminal of said first power source and said substrate ground well in the manner of being a reverse bias direction; and

a second protection diode connected between said source terminal of said second power source and said substrate ground well in the manner of being a reverse direction;

whereby interference between said first and second power sources is prevented by said first and second protection diodes;

wherein said first protection diode and/or said second protection diode comprises or respectively comprise any or combination of a diode, bipolar transistors which are connected with each other in a diode connection, and metal oxide layer semiconductor (MOS) transistors which are connected with each other in a diode connection.

4. The semiconductor device according to claim 1:

wherein

at least any of said first well, said second well, said deep well and said substrate ground well is formed by an epitaxial growth.

2. A semiconductor device comprising:

a semiconductor substrate having at least a first well and a second well which are electrically divided from each other;

a first electric circuit formed in said first well and connected to a first circuit power source through a source terminal;

a second electric circuit formed in said second well and connected to a second circuit power source through a source terminal;

a substrate ground well formed on said semiconductor substrate and connected to a third circuit power source which outputs a stable reference potential;

a first protection diode connected between said source terminal of said first power source and said substrate ground well in the manner of being a reverse bias direction; and

a second protection diode connected between said source terminal of said second power source and said substrate ground well in the manner of being a reverse direction;

whereby interference between said first and second power sources is prevented by said first and second protection diodes;

a semiconductor substrate formed from a P-type semiconductor in which a hole density is larger than a conduction electron density;

a digital circuit as said first electric circuit provided in a first deep N-well formed on said semiconductor substrate by an N-type high concentration semiconductor in which a conduction electron density is larger than a hole density, and said digital circuit being connected through said power source terminal to a digital circuit power source;

an analog circuit as said second electric circuit provided with electrically insulated to said digital circuit in a second deep N-well formed on said semiconductor substrate by said N-type high concentration semiconductor, and said analog circuit being connected through said power source terminal to an analog circuit power source;

a substrate grounding first P-well formed by said P-type semiconductor on said semiconductor substrate for grounding and being connected through a ground terminal exclusively using for said substrate to said third circuit power source for adding a stable reference potential;

said first protection diode connected between said power source terminal of said digital circuit power source and said substrate grounding first P-well in the manner of making a reverse bias; and

said

said second protection diode connected between said power source terminal of said analog circuit power source and said substrate grounding first P-well in the manner of making a reverse bias.

5. The semiconductor device according to claim 2:

wherein

said substrate grounding first P-well has two N⁺ regions which are made of a high concentration N-type semiconductor, one of which is connected in parallel to a connection line between said digital circuit power source and said digital circuit so to be said first protection diode, and the other of which is connected in parallel to a connection line between said analog circuit power source and said analog circuit so as to be said second protection diode.

6. The semiconductor device according to claim 2:

wherein

said substrate grounding first P-well has to fourth N⁺ regions formed by said high concentration N-type semiconductor, said first N⁺ region is connected in parallel to a connection line between said digital circuit power source and said digital circuit, said second N⁺ region is connected in parallel to a connection line between said analog circuit power source and said analog circuit, said third N⁺ region is connected a first MOS transistor, and said fourth N⁺ region is connected to a second MOS transistor; and

wherein

a first diode element and a first bipolar transistor constructed by said first and third N⁺ regions and said first MOS transistor function as said first protection diode, and a second diode element and a second bipolar transistor constructed by said second and fourth N⁺ regions and said second MOS transistor function as said protection diode.

7. The semiconductor device according to claim 2:

wherein

said substrate grounding first P-well has fifth to eighth N⁺ regions formed by said high concentration N-type semiconductor, said fifth N⁺ region is connected in parallel to a connection line between said digital circuit and said digital circuit so as to form a third bipolar transistor, said sixth N⁺ region is connected in parallel to a ground so as to form a fourth bipolar transistor, said seventh N⁺ region is connected in parallel to a connection line between said analog circuit and analog power source so as to form a third diode element, and said eighth N⁺ region is connected to a connection line between said digital circuit and digital power source so as to form a fourth diode element; and

wherein

said third bipolar transistor and said diode element function as said first protection diode, and a fourth bipolar transistor and fourth diode element function as said second protection diode.

8. The semiconductor device according to claim 2:

wherein

said substrate grounding first P-well has fifth to eighth N⁺ regions formed by said high concentration N-type semiconductor, said fifth N⁺ region is connected in parallel to a connection line between said digital circuit and said digital circuit and also connected to a third MOS transistor, said sixth N⁺ region is connected in parallel to a connection line between said analog circuit and said analog ground and also connected to a fourth MOS transistor, said seventh N⁺ region is connected in parallel to a connection line between said analog circuit and analog power source so as to form a third diode element, and said eighth N⁺ region is connected in parallel to a connection line between said digital circuit and digital power source so as to form a fourth diode element; and

wherein

said third MOS transistor and said third diode element function as said first protection diode, and a fourth MOS transistor and said fourth diode element function as said second protection diode.

9. The semiconductor device according to claim 2:

wherein

a first MOS transistor functioning as said first protection diode is connected in the manner of making a reverse bias in parallel to a connection line between said digital circuit power source and a P⁺ region which is formed through an N-well on said first deep N-well including said digital circuit; and

a second MOS transistor functioning as said second protection diode is connected in the manner of making a reverse bias in parallel to a connection line between said analog circuit power source and a P⁺ region which is formed through an N-well on said deep N-well including said analog circuit.

10. The semiconductor device according to claim 2:

wherein

a first MOS transistor is connected in the manner of making a reverse bias in parallel to a connection line between said substrate grounding P-well and an N⁺ region which is formed trough a P-well in said first deep N-well in which said digital circuit is formed, and said first MOS transistor functions as said first protection diode; and

a second MOS transistor is connected in the manner of making a reverse bias in parallel to a connection line between said substrate grounding P-well and an N⁺ region which is formed through a P-well in said second deep N-well in which said analog circuit is formed, and second MOS transistor functions as second protection diode.

11. The semiconductor device according to claim 2:

wherein

said second deep N-well for said analog circuit is formed in a square shape in a plan view at the center portion of said P-type substrate, said substrate grounding P-well is formed around said analog circuit, and said first deep N-well for said digital circuit is formed further around said substrate grounding P-well.

3. A semiconductor device comprising:

a semiconductor substrate having at least a first well and a second well which are electrically divided from each other;

first electric circuit formed in said first well and connected to a first circuit power source through a source terminal;

a second electric circuit formed in said second well and connected to a second circuit power source through a source terminal;

a substrate ground well formed on said semiconductor substrate and connected to a third circuit power source which outputs a stable reference potential;

a first protection diode connected between said source terminal of said first power source and said substrate ground well in the manner of being a reverse bias direction; and

a second protection diode connected between said source terminal of said second power source and said substrate ground well in the manner of being a reverse direction;

whereby interference between said first and second power sources is prevented by said first and second protection diodes;

a semiconductor substrate formed from an N-type semiconductor in which a conduction electron density is larger than a hole density;

a digital circuit as said first electric circuit provided in a second deep P-well formed on said semiconductor substrate by a P-type high concentration semiconductor in which a hole density is larger than a conduction electron density, and said digital circuit being connected through said power source terminal to a digital circuit ground;

an analog circuit as said second electric circuit provided with electrically insulated to said digital circuit in a third deep P-well formed on said semiconductor substrate by said P-type high concentration semiconductor, and said analog circuit being connected through said power source terminal to an analog circuit ground;

a substrate grounding third N-well formed by said N-type semiconductor on said semiconductor substrate for grounding and being connected through a ground terminal exclusively using for said substrate to said third circuit power source for adding a stable reference potential;

said first protection diode connected between said power source terminal of said digital circuit power source and said substrate grounding third N-well in the manner of making a reverse bias; and

said second protection diode connected between said power source terminal of said analog circuit power source and said substrate grounding third N-well in the manner of making a reverse bias.

12. The semiconductor device according to claim 3:

wherein

two P⁺ regions is made of a high concentration p-type semiconductor on a substrate grounding third N-well, one of which is connected in parallel to a connection line between said digital circuit power source and said digital circuit so as to form said first protection diode, the other of which is connected in parallel to a connection line between said analog circuit power source and said analog circuit so as to form said second protection diode.

13. The semiconductor device according to claim 3, wherein

said substrate grounding third N-well has first to fourth P⁺ regions formed by a high concentration P-type semiconductor, said first P⁺ region is connected in parallel to a connection line between said digital circuit and said digital ground, said second P⁺ region is connected in parallel to a connection line between said analog circuit and said analog ground, said third P⁺ region is connected to a first MOS transistor, and said fourth P⁺ region is connected to a second MOS transistor;

and wherein

a first diode element and a first bipolar transistor constructed from said first and third P⁺ regions and said first MOS transistor function as said first protection diode, and a second diode element and a second bipolar transistor constructed from said second and fourth P⁺ regions and said second MOS transistor function as said second protection diode.