Packaging and interconnect system for integrated circuits

• US 5,796,164 A
• Filed: 03/25/1996
• Issued: 08/18/1998
• Est. Priority Date: 05/11/1993
• Status: Expired due to Fees

• Current Assignee: Kulicke and Soffa Industries Incorporated
• Original Assignee: Micromodule Systems, Inc.
• Inventors: Grove, Michael I., McGraw, Mark T., Ho, Chung W., Min, Byoung-Youl, Robinette, William C. Jr., Griswold, Bradley L.
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): CLARK, JASMINE JHIHAN B
• Application Number:
  US08/621,563
• Time in Patent Office: 876 Days
• Field of Search: 257/723, 257/679, 257/773, 257/787, 257/767, 257/685
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/05599 Material
• CPC Class Codes: H01L 2224/45015 being circular
• CPC Class Codes: H01L 2224/45099 Material
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/85399 Material
• CPC Class Codes: H01L 23/24 solid or gel at the normal operating temperature of the device H01L23/3135 takes precedence
• CPC Class Codes: H01L 23/3121 a substrate forming part of the encapsulation
• CPC Class Codes: H01L 23/3128 the substrate having spherical bumps for external connection
• CPC Class Codes: H01L 23/5387 Flexible insulating substrates H01L23/5388 takes precedence
• CPC Class Codes: H01L 23/5389 the chips being integrally enclosed by the interconnect and support structures
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 25/0652 the devices being arranged next and on each other, i.e. mixed assemblies
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01057 Lanthanum [La]
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01087 Francium [Fr]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 : Integrated circuits
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/207 : Diameter ranges

Abstract

A thin MCM packaging structure and technique is provided in which a thin film decal interconnect circuit is fabricated on a thin aluminum wafer. The thin-film decal interconnect employs Au metallurgy for bonding and comprises a bond pad/ground plane layer, topside pads, and one or more routing layers. The top routing layer also acts as the pad layer along the edge of the interconnect structure. The underside of the decal interconnect structure is provided with metal pads for attachment to conventional aluminum or gold I/O pads on one surface of the integrated circuit die. A thermosonic bonding system is used to bond the die pads to the pads. The aluminum wafer is selectively removed forming one or more cavities to hold one or more die to be mounted on the MCM structure. The die are oriented with their pads in contact with contact pads on the thin-film decal interconnect to which they are bonded and the cavities are filled with a liquid encapsulant and cured. A leadframe has inner bond leads electrically bonded to bonding pads of the thin film multilayer interconnect circuit disposed about a periphery thereof and a multi-layer laminate board is mechanically bonded over the thin film multilayer interconnect circuit and over the inner bond leads of the lead frame and has a first layer including conductive pads extending outward from about an inner periphery thereof, and a second layer including apertures aligned with outwardly extending portions of the conductive pads.

Claims

1. A multichip module packaging structure comprising:

a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors;

at least one integrated circuit die having first and second surfaces and disposed entirely within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one integrated circuit die including a plurality of I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one integrated circuit die aligned so as to mate said plurality of I/O connection pads with said plurality of first bonding pads, said I/O connection pads electrically connected to said first bonding pads.

2. The multichip module packaging structure of claim 1 wherein said I/O connection pads are electrically connected to said first bonding pads by solder ball reflow.

3. The multichip module packaging structure of claim 1 wherein said I/O connection pads are electrically connected to said first bonding pads by gold to gold with adhesive attach.

4. The multichip module packaging structure of claim 1 wherein said I/O connection pads are electrically connected to said first bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

5. A multichip module packaging structure comprising:

a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors;

at least one first integrated circuit die having first and second surfaces and disposed entirely within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die including a plurality of first I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die aligned so as to mate said plurality of I/O connection pads with said plurality of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads; and

at least one second integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one second integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one second integrated circuit die, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit.

6. The multichip module packaging structure of claim 5 wherein said I/O connection pads are electrically connected to said first bonding pads by solder ball reflow.

7. The multichip module packaging structure of claim 5 wherein said I/O connection pads are electrically connected to said first bonding pads by gold to gold with adhesive attach.

8. The multichip module packaging structure of claim 5 wherein said I/O connection pads are electrically connected to said first bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

9. A multichip module packaging structure comprising:

a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including a plurality of chip mounting cavities formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors;

a plurality of integrated circuit dice having first and second surfaces, one of said integrated circuit dice disposed within each of said plurality of chip mounting cavities on said first surface of said thin film multilayer interconnect circuit, each of said integrated circuit dice including a plurality of I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, each of said integrated circuit dice aligned so that its plurality of I/O connection pads align with ones of first bonding pads, said I/O connection pads electrically connected to said first bonding pads.

10. The multichip module packaging structure of claim 9 wherein said I/O connection pads are electrically connected to said first bonding pads by solder ball reflow.

11. The multichip module packaging structure of claim 9 wherein said I/O connection pads are electrically connected to said first bonding pads by gold to gold with adhesive attach.

12. The multichip module packaging structure of claim 9 wherein said I/O connection pads are electrically connected to said first bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

13. The multichip module packaging structure of claim 9 further including a layer of encapsulant disposed over said plurality of integrated circuit dice in said at least one chip mounting cavity.

14. A multichip module packaging structure comprising:

a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including a plurality of chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors;

a plurality of integrated circuit dice having first and second surfaces, one of said integrated circuit dice disposed within each of said chip mounting cavities on said first surface of said thin film multilayer interconnect circuit, each of said first integrated circuit dice including a plurality of first I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, each of said integrated circuit dice aligned so that its plurality of I/O connection pads align with ones of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads; and

at least one second integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one second integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one second integrated circuit die, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit.

15. The multichip module packaging structure of claim 14 wherein said I/O connection pads are electrically connected to said first bonding pads by solder ball reflow.

16. The multichip module packaging structure of claim 14 wherein said I/O connection pads are electrically connected to said first bonding pads by gold to gold with adhesive attach.

17. The multichip module packaging structure of claim 14 wherein said I/O connection pads are electrically connected to said first bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

18. The multichip module packaging structure of claim 14 further including a layer of encapsulant disposed over said first and second integrated circuit dice.

19. The multichip module packaging structure of claim 14 wherein said at least one second integrated circuit die comprises a plurality of integrated circuit dice.

20. A multichip module packaging structure comprising:

a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors;

at least one first integrated circuit die having first and second surfaces and disposed within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die including a plurality of first I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die aligned so as to mate said plurality of I/O connection pads with said plurality of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads;

at least one second integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one second integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one second integrated circuit die, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit;

a leadframe having outer leads extending outside of a periphery of said multichip module packaging structure and having inner bond leads electrically bonded to ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit disposed about a periphery thereof;

a multi-layer laminate board mechanically bonded over said second surface of said thin film multilayer interconnect circuit and over said inner bond leads of said lead frame, said multilayer laminate board having a first layer including conductive pads extending outward from about an inner periphery thereof, said multilayer laminate board further having a second layer including apertures formed therethrough, said apertures aligned with outwardly extending portions of said conductive pads and exposing an upper surface of said conductive pads.

21. The multichip module packaging structure of claim 20 wherein said I/O connection pads are electrically connected to said first bonding pads by solder ball reflow.

22. The multichip module packaging structure of claim 20 wherein said I/O connection pads are electrically connected to said first bonding pads by gold to gold with adhesive attach.

23. The multichip module packaging structure of claim 20 wherein said I/O connection pads are electrically connected to said first bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

24. The multichip module packaging structure of claim 20 further including a layer of encapsulant disposed over said at least one first and second integrated circuit die.

25. A multichip module packaging structure comprising:

a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors;

at least one first integrated circuit die disposed in said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die having a first surface bonded to said first surface of said thin film multilayer interconnect circuit in a position such that said plurality of first bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one first integrated circuit die, said at least one first integrated circuit die including a plurality of first I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of first I/O connection pads wire bonded to corresponding ones of said plurality of first bonding pads of said thin film multilayer interconnect circuit;

at least one second integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one second integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one second integrated circuit die, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit; and

a leadframe having outer leads extending outside of a periphery of said multichip module packaging structure and having inner bond leads electrically bonded to ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit disposed about a periphery thereof;

a multi-layer laminate board mechanically bonded over said second surface of said thin film multilayer interconnect circuit and over said inner bond leads of said lead frame, said multilayer laminate board having a first layer including conductive pads extending outward from about an inner periphery thereof, said multilayer laminate board further having a second layer including apertures formed therethrough, said apertures aligned with outwardly extending portions of said conductive pads and exposing an upper surface of said conductive pads.

26. The multichip module packaging structure of claim 25 further including a layer of encapsulant disposed over said at least one first and second integrated circuit die.

28. The multichip module packaging structure of claim 26 wherein said first I/O connection pads are electrically connected to said first bonding pads by solder ball reflow.

29. The multichip module packaging structure of claim 26 wherein said first I/O connection pads are electrically connected to said first bonding pads by gold to gold with adhesive attach.

30. The multichip module packaging structure of claim 26 wherein said first I/O connection pads are electrically connected to said first bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

31. The multichip module packaging structure of claim 26 further including a layer of encapsulant disposed over said plurality of integrated circuit dice.

33. The multichip module packaging structure of claim 31 wherein said first I/O connection pads and said first bonding pads, and said third I/O connection pads and said third bonding pads are electrically connected by solder ball reflow.

34. The multichip module packaging structure of claim 31 wherein said first I/O connection pads are electrically bonded to said first bonding pads, and said third I/O connection pads are electrically bonded to said third bonding pads by gold to gold with adhesive attach.

35. The multichip module packaging structure of claim 31 wherein said first I/O connection pads are electrically bonded to said first bonding pads, and said third I/O connection pads are electrically bonded to said third bonding pads by particle impregnated bump to aluminum pad with adhesive attach.

36. The multichip module packaging structure of claim 31 further including a layer of encapsulant disposed over said plurality of integrated circuit dice.

27. A multichip module packaging structure comprising:

a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors;

at least one first integrated circuit die disposed entirely within said at least one chip mounting cavity on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die having first and second surfaces, wherein on said first surface thereof, a plurality of first I/O connection pads in contact with said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die aligned for mating said plurality of first I/O connection pads with a plurality of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads;

at least one second integrated circuit die disposed on said second surface of said at least one first integrated circuit die, said at least one second integrated circuit die having a first surface bonded to said second surface of said at least one first integrated circuit die in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one first integrated circuit die and said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit; and

at least one third integrated circuit die disposed on said second surface of said thin film multilayer interconnect circuit, said at least one third integrated circuit die having a first surface bonded to said second surface of said thin film multilayer interconnect circuit in a position such that a plurality of third bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one third integrated circuit die, said at least one third integrated circuit die including a plurality of third I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of third I/O connection pads wire bonded to corresponding ones of said plurality of third bonding pads of said thin film multilayer interconnect circuit.

32. A multichip module packaging structure comprising:

a thin film multilayer interconnect circuit disposed on a baseplate, said baseplate including at least one chip mounting cavity formed therein, said thin film multilayer interconnect circuit comprising a layer including a plurality of first bonding pads disposed on a first surface thereof, a layer including a plurality of second bonding pads disposed on a second surface thereof, and at least one routing layer including a plurality of routing conductors;

at least one first integrated circuit die disposed within said at least one chip mounting cavity and on said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die having first and second surfaces, wherein a plurality of first I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one first integrated circuit die aligned for mating said plurality of first I/O connection pads with said plurality of first bonding pads, said first I/O connection pads electrically connected to said first bonding pads;

at least one second integrated circuit die disposed within said at least one chip mounting cavity, said at least one second integrated circuit die having a first surface bonded to said second surface of said at least one first integrated circuit in a position such that said plurality of second bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one first integrated circuit die and of said at least one second integrated circuit, said at least one second integrated circuit die including a plurality of second I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of second I/O connection pads wire bonded to corresponding ones of said plurality of second bonding pads of said thin film multilayer interconnect circuit;

at least one third integrated circuit die disposed on said first surface of said thin film multilayer interconnect circuit, said at least one third integrated circuit die having first and second surfaces, wherein a plurality of third I/O connection pads disposed on said first surface thereof in contact with said first surface of said thin film multilayer interconnect circuit, said at least one third integrated circuit die aligned for mating said plurality of third I/O connection pads with said plurality of first bonding pads, said third I/O connection pads electrically connected to said first bonding pads; and

at least one fourth integrated circuit die having a first surface bonded to said second surface of said at least one third integrated circuit die in a position such that said plurality of fourth bonding pads of said thin film multilayer interconnect circuit are disposed about the periphery of said at least one third integrated circuit die and said at least one fourth integrated circuit die, wherein said at least one fourth integrated circuit die having a plurality of fourth I/O connection pads disposed on a second surface thereof opposed to said first surface thereof, ones of said plurality of fourth I/O connection pads wire bonded to corresponding ones of said plurality of fourth bonding pads of said thin film multilayer interconnect circuit.