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High-precision voltage dependent timing delay circuit

  • US 5,796,284 A
  • Filed: 12/16/1996
  • Issued: 08/18/1998
  • Est. Priority Date: 07/31/1995
  • Status: Expired due to Term
First Claim
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1. A timing delay circuit which comprises delay means (1) for providing an output signal (3) in response to an input signal (2), where said output signal is delayed with respect to said input signal, said delay varying with a supply voltage (Vdd) by which said circuit is powered;

  • and circuit means (78) with a switching threshold (21) which are connected to said output of said delay means for receiving said output signal (3), said timing delay circuit characterized by switching means (14, 34, 43,

         70) for providing a current sink element (NFET 14, 34, or

         70) or a current source element (PFET

         43) coupled to the output of the delay means (1), said current sink element sinking current from said output signal (3) upon a rising edge of said output signal (3) of said delay means (1) and said current source element sourcing current to said output signal (3) of said delay means upon a falling edge of said output signal (3) of said delay means (1), said switching means being enabled by an adjustable control voltage (71) which varies in proportion to said supply voltage, said switching means being enabled if said supply voltage exceeds a minimum value and said switching means being disabled if said supply voltage is below said minimum value , said enabled switching means further delaying the output signal (3) of the delay means by increasing the time required for the rising or falling edge of said output signal to respectively rise or fall to the switching threshold of the circuit means.

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