High-precision voltage dependent timing delay circuit

• US 5,796,284 A
• Filed: 12/16/1996
• Issued: 08/18/1998
• Est. Priority Date: 07/31/1995
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Loehlein, Wolfdieter, Clemen, Rainer, Mielich, Harald
• Primary Examiner(s): TRAN, TOAN V
• Application Number:
  US08/765,416
• Time in Patent Office: 610 Days
• Field of Search: 327/263, 327/264, 327/276, 327/277, 327/278, 327/281, 327/261, 327/51, 327/52, 327/54, 327/55, 327/53, 327/57, 327/333
• US Class Current: 327/264
• CPC Class Codes: G11C 7/06 Sense amplifiers; Associated circuits , e.g. timing or triggering circuits
• CPC Class Codes: G11C 7/067 Single-ended amplifiers
• CPC Class Codes: G11C 7/22 Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management
• CPC Class Codes: H03K 19/00323 Delay compensation
• CPC Class Codes: H03K 5/133 using a chain of active delay devices

Abstract

For high-speed single-ended sensing of the small signal delivered from a (static) RAM or ROM cell, a voltage dependent timing delay circuit is disclosed which prevents early triggering of the set signal of the sense amplifier (SSA 66) when applying a high voltage screen test (i.e. 1.5 times V_DD) to the cell. The timing of the SSA signal is achieved by a high precision delay chain comprising inverters, which is loaded by a voltage dependent current sink (70) coupled to the output of the chain. The inverter delay chain controls the input (SE0) for a driver for the SSA line (66). The current sink may be a pull down NFET (70) which is only activated when the supply voltage is above a determined switching threshold therefor. The gate voltage of the NFET is controlled by a bias control circuit (72) in such a manner that during operation at typical voltage levels, the NFET is deactivated, whereas at higher operating voltage levels (such as 1.5 * V_DD) the NFET is turned on, thereby sinking current from the input (SE0) to the driver for the SSA line. The SSA signal is consequently delayed preventing the early triggering thereof.

Claims

1. A timing delay circuit which comprises delay means (1) for providing an output signal (3) in response to an input signal (2), where said output signal is delayed with respect to said input signal, said delay varying with a supply voltage (Vdd) by which said circuit is powered;

and circuit means (78) with a switching threshold (21) which are connected to said output of said delay means for receiving said output signal (3), said timing delay circuit characterized by switching means (14, 34, 43,

     70) for providing a current sink element (NFET 14, 34, or

     70) or a current source element (PFET

     43) coupled to the output of the delay means (1), said current sink element sinking current from said output signal (3) upon a rising edge of said output signal (3) of said delay means (1) and said current source element sourcing current to said output signal (3) of said delay means upon a falling edge of said output signal (3) of said delay means (1), said switching means being enabled by an adjustable control voltage (71) which varies in proportion to said supply voltage, said switching means being enabled if said supply voltage exceeds a minimum value and said switching means being disabled if said supply voltage is below said minimum value , said enabled switching means further delaying the output signal (3) of the delay means by increasing the time required for the rising or falling edge of said output signal to respectively rise or fall to the switching threshold of the circuit means.

2. Delay circuit as in claim 1, further characterized by means (72) for generating said control voltage (71) dependent on said supply voltage (Vdd).

7. Delay circuit as in claim 2, characterized in that said means (72) for generating said control voltage comprises a stack of n diodes (72).

8. Delay circuit as in claim 7, characterized in that said stack of diodes (72) comprises a series connection of n NMOS field effect transistors, where each of said transistors has a gate and a drain interconnected to form a diode.

3. A timing delay circuit which comprises delay means (1) for providing an output signal (3) in response to an input signal (2), where said output signal is delayed with respect to said input signal, said delay varying with a supply voltage (Vdd) by which said circuit is powered;

and circuit means (78) with a switching threshold (21) which are connected to said output of said delay means for receiving said output signal (3), said timing delay circuit characterized by switching means (14, 34, 43,

     70) for providing a current mink element (NFET 14, 34, or

     70) or a current source element (pFET

     43) coupled to the output of the delay means (1), said current sink element sinking current from said output signal (3) upon a rising edge of said output signal (3) of said delay means (1) and said current source element sourcing current to said output signal (3) of said delay means upon a falling edge of said output signal (3) of said delay means (1), said switching means being enabled by an adjustable control voltage (71) which is dependent upon said supply voltage, said enabled switching means further delaying said output signal (3) of said delay means, and wherein said timing delay circuit further includes clock means (82) for providing a clock signal to said switching means for controlling the level of the adjustable control voltage of said switching means.

4. Delay circuit as in claims 3, characterized in that said delay means comprises an inverting or a non-inverting inverter delay chain (1, 11, 31-33, 67, 68) and that said switching means (14, 34, 43, 70) is connected to an output (FIGS. 4a, b) of a stage of said delay chain depending on whether the output signal of said stage is rising or falling.

5. A delay circuit as in claim 3 characterized in that said current sink element (14, 34, 70) comprises a NMOS field effect transistor (70) with said adjustable control voltage applied to a gate (71) of said transistor,

said control voltage being close to a threshold voltage for said NMOS transistor, if the level of said supply voltage is at a determined minimum level for said supply voltage, and

said control voltage being larger than said threshold voltage, if the level of said supply voltage is greater than the determined minimum level for said supply voltage.

6. A delay circuit as in claim 3 characterized in that said current source element (43) comprises a PMOS field effect transistor (43) with said adjustable control voltage applied to a gate of said transistor,

said control voltage being close to the difference of said supply voltage and said threshold voltage of said PMOS transistor, if the level of said supply voltage is at a determined minimum level for said supply voltage, and

said control voltage being smaller than said difference, if the level of said supply voltage is less than the determined minimum level for said supply voltage.

11. A timing delay circuit as in claim 3 in a high speed memory array, characterized in that said circuit means includes a sense amplifier (78) for sensing and amplifying a signal which is delivered by a memory cell (63) of said memory array when selected for a read operation;

wherein said delay means is triggered from a sample word line(80) and provides a set signal (SSA) for said sense amplifier; and

wherein said set signal is delayed by said switching means when said supply voltage exceeds a nominal operation voltage level.

12. A timing delay circuit as in claim 11 for single-ended sensing in a fast multi-port SRAM.

13. A timing delay circuit as in claim 11 characterized in that said timing delay circuit further comprises a 2-way NAND gate (64) coupled to the output of said delay means for receiving said output signal (3) said NAND gate having a set input and a reset input and an output coupled to an inverting buffer (65) for driving a control line for said sense amplifier (78).

14. A timing delay circuit as in claim 13, characterized in that said set input of said NAND gate (64) is connected to a non-inverting delay chain (67, 68) of inverters which is triggered from said sample word line (80), and said reset input of said NAND gate which initiates deactivation of said sense amplifier signal is fed by a second inverter chain.

15. A timing delay circuit as in claim 11, characterized in that a gate voltage (71) of said current element sink/source (70) is adjusted by a number of NMOS diodes (72) being inserted between said supply voltage and a gate of said current element sink/source.

16. A timing delay circuit as in claim 11, characterized in that at said nominal supply voltage said current sink element remains just turned off.

17. A timing delay circuit as in claim 14, characterized in that said current sink element (70) comprises the same current drive capability as a PMOS transistor at the output of an inverter stage (68), where said current sink element is connected.

9. In a timing delay circuit comprising

delay means (1) for providing an output signal (3) in response to an input signal (2), where said output signal is delayed with respect to said input signal, said delay varying with a supply voltage (Vdd) by which said circuit is powered;

circuit means (78) with a switching threshold (21) which are connected to said output of said delay means; and

switching means (14, 34, 43,

     70) for providing a current sink/source dependent on a rising/falling edge of said output signal, which is connected to said output of said delay means, and which is switched by a control voltage (71) dependent on said supply voltage;

a method for precisely adjusting said timing delay dependent on said supply voltage, characterized by the steps of;

determining a threshold voltage for said switching means; and

switching said switching means dependent on whether said supply voltage exceeds a minimum value and whether said control voltage becomes larger than said threshold voltage (FIG.

     3).

10. In a timing delay circuit comprising

delay means (1) for providing an output signal (3) in response to an input signal (2), where said output signal is delayed with respect to said input signal, said delay varying with a supply voltage (Vdd) by which said circuit is powered;

circuit means (78) with a switching threshold (21) which are connected to said output of said delay means; and

switching means (14, 34, 43,

     70) for providing a current sink/source dependent on a rising/falling edge of said output signal, which is connected to said output of said delay means, and which is switched by a control voltage (71) dependent on said supply voltage;

a method for precisely adjusting said timing delay dependent on said supply voltage, characterized by the steps of;

determining a threshold voltage for said switching means; and

switching said switching means dependent on whether said supply voltage exceeds a minimum value and whether said control voltage becomes smaller than the difference between said supply voltage and said threshold voltage (FIG.

     3).