Microcontroller with firmware selectable oscillator trimming

• US 5,796,312 A
• Filed: 05/24/1996
• Issued: 08/18/1998
• Est. Priority Date: 05/24/1996
• Status: Expired due to Term

• Current Assignee: Microchip Technology Incorporated
• Original Assignee: Microchip Technology Incorporated
• Inventors: Bingham, Gregory C., Hull, Richard L.
• Primary Examiner(s): Grimm, Siegfried H.
• Application Number:
  US08/644,914
• Time in Patent Office: 816 Days
• Field of Search: 331/44, 331/177 R, 331/175, 331/143
• US Class Current: 331/44
• CPC Class Codes: G06F 1/08 Clock generators with changeable or programmable clock frequency
• CPC Class Codes: G06F 15/7814 Specially adapted for real time processing, e.g. comprising hardware timers
• CPC Class Codes: H03K 17/164 using parallel switching arrangements
• CPC Class Codes: H03K 3/0231 Astable circuits H03K3/0315 takes precedence
• CPC Class Codes: Y02D 10/00 Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A microcontroller circuit having firmware selectable oscillator trimming includes, in combination, a microcontroller, an oscillator located within the microcontroller for providing a system clock signal for the microcontroller, and a memory portion for providing trimming data to the oscillator for trimming frequency of the system clock. The microcontroller circuit includes microcontroller logic which has the trimming data stored therein for transfer to the memory portion. Additionally, the microcontroller logic permits the user to alter the trimming data after it has been transferred to the memory portion, thereby permitting the user to alter the amount of modification of the system clock frequency from the amount associated with the trimming data.

Claims

1. A microcontroller circuit having firmware selectable oscillator trimming comprising, in combination:

a microcontroller;

oscillator means located within said microcontroller for providing a system clock signal for said microcontroller wherein said oscillator means generating an oscillatory signal of a predetermined frequency across a series resistor-capacitor (RC) network by ensuring that the oscillatory signal accurately oscillates between first and second voltages generated from a supply voltage source where the frequency of oscillation is determined by both the time constant of the RC network and the difference between the first and second voltages, said oscillator means comprising, in combination;

charging-discharging means for discharging a voltage across the capacitor commencing when voltage of the oscillatory signal exceeds a first threshold voltage and for charging said voltage across the capacitor commencing when voltage of the oscillatory signal falls below a second threshold voltage;

first sampling means coupled to said charging-discharging means for obtaining a first sampled voltage of the oscillatory signal upon commencement of discharging of said voltage across the capacitor;

first compensation means coupled to said first sampling means for adjusting said first threshold voltage to be the first voltage modified by a voltage difference between the first voltage and said first sampled voltage;

second sampling means coupled to said charging-discharging means for obtaining a second sampled voltage of the oscillatory signal upon commencement of charging of said voltage across the capacitor;

second compensation means coupled to said second sampling means for adjusting said second threshold voltage to be the second voltage modified by a voltage difference between the second voltage and said second sampled voltage; and

differential voltage setting means coupled to said second compensation means for selecting the second voltage from a plurality of different possible voltages and thereby selecting a voltage difference between the first and second voltages; and

memory means coupled to said oscillator means for providing signals to said oscillator means for trimming frequency of said system clock.

2. The microcontroller circuit of claim 1 further including microcontroller logic means having trimming data stored therein for providing said trimming data to said memory means.

3. The microcontroller circuit of claim 2 wherein said microcontroller logic means also includes oscillator control means therein for selecting between use of said oscillator means internal to said microcontroller for said system clock and use of an external oscillator source for said system clock.

4. The microcontroller circuit of claim 3 further including oscillator logic means coupled to said microcontroller logic means, to said oscillator means, and to said external oscillator source for providing, in response to receipt of a signal from said oscillator control means, said system clock to said microcontroller from one of said oscillator means and said external oscillator source.

5. The microcontroller circuit of claim 2 wherein said memory means comprises Static Random Access Memory (SRAM) having control register means for storing said trimming data and supplying said trimming data to said oscillator means.

6. The microcontroller circuit of claim 5 further including SRAM address, data, read, and write lines between said microcontroller logic means and said SRAM.

7. The microcontroller circuit of claim 5 further including a plurality of lines coupling said control register means with said oscillator means for transferring said trimming data to said oscillator means.

8. The microcontroller circuit of claim 1 wherein said memory means is located within said microcontroller.

9. The microcontroller circuit of claim 2 further including trimming data adjustment means within said microcontroller logic means for altering said trimming data after said trimming data has been transferred to said memory means.

10. A method of operating a microcontroller circuit having firmware selectable oscillator trimming comprising the steps of:

providing a microcontroller;

providing a system clock signal to said microcontroller from oscillator means located within said microcontroller, said oscillator means generating an oscillatory signal of a predetermined frequency across a series resistor-capacitor (RC) network by ensuring that the oscillatory signal accurately oscillates between first and second voltages generated from a supply voltage source where the frequency of oscillation is determined by both the time constant of the RC network and the difference between the first and second voltages, said oscillator means comprising, in combination;

charging-discharging means for discharging a voltage across the capacitor commencing when voltage of the oscillatory signal exceeds a first threshold voltage and for charging said voltage across the capacitor commencing when voltage of the oscillatory signal falls below a second threshold voltage;

first sampling means coupled to said charging-discharging means for obtaining a first sampled voltage of the oscillatory signal upon commencement of discharging of said voltage across the capacitor;

first compensation means coupled to said first sampling means for adjusting said first threshold voltage to be the first voltage modified by a voltage difference between the first voltage and said first sampled voltage;

second sampling means coupled to said charging-discharging means for obtaining a second sampled voltage of the oscillatory signal upon commencement of charging of said voltage across the capacitor;

second compensation means coupled to said second sampling means for adjusting said second threshold voltage to be the second voltage modified by a voltage difference between the second voltage and said second sampled voltage; and

differential voltage setting means coupled to said second compensation means for selecting the second voltage from a plurality of different possible voltages and thereby selecting a voltage difference between the first and second voltages; and

providing memory means coupled to said oscillator means for providing signals to said oscillator means for trimming frequency of said system clock.

11. The method of claim 10 further including the step of providing microcontroller logic means having trimming data stored therein for providing said trimming data to said memory means.

12. The method of claim 11 wherein said step of providing said microcontroller logic means also includes the step of providing oscillator control means therein for selecting between use of said oscillator means internal to said microcontroller for said system clock and use of an external oscillator source for said system clock.

13. The method of claim 12 further including the step of providing oscillator logic means coupled to said microcontroller logic means, to said oscillator means, and to said external oscillator source for providing, in response to receipt of a signal from said oscillator control means, said system clock to said microcontroller from one of said oscillator means and said external oscillator source.

14. The method of claim 11 wherein said step of providing said memory means comprises the step of providing Static Random Access Memory (SRAM) having control register means for storing said trimming data and supplying said trimming data to said oscillator means.

15. The method of claim 14 further including the step of providing SRAM address, data, read, and write lines between said microcontroller logic means and said SRAM.

16. The method of claim 14 further including the step of providing a plurality of lines coupling said control register means with said oscillator means for transferring said trimming data to said oscillator means.

17. The method of claim 10 wherein said memory means is located within said microcontroller.

18. The method of claim 11 further including the step of providing trimming data adjustment means within said microcontroller logic means for altering said trimming data after said trimming data has been transferred to said memory means.

19. A microcontroller circuit having firmware selectable oscillator trimming comprising, in combination:

a microcontroller;

oscillator means located within said microcontroller for providing a system clock signal for said microcontroller wherein said oscillator means generating an oscillatory signal of a predetermined frequency across a series resistor-capacitor (RC) network by ensuring that the oscillatory signal accurately oscillates between first and second voltages generated from a supply voltage source where the frequency of oscillation is determined by both the time constant of the RC network and the difference between the first and second voltages, said oscillator means comprising, in combination;

charging-discharging means for discharging a voltage across the capacitor commencing when voltage of the oscillatory signal exceeds a first threshold voltage and for charging said voltage across the capacitor commencing when voltage of the oscillatory signal falls below a second threshold voltage;

first sampling means coupled to said charging-discharging means for obtaining a first sampled voltage of the oscillatory signal upon commencement of discharging of said voltage across the capacitor;

first compensation means coupled to said first sampling means for adjusting said first threshold voltage to be the first voltage modified by a voltage difference between the first voltage and said first sampled voltage;

second sampling means coupled to said charging-discharging means for obtaining a second sampled voltage of the oscillatory signal upon commencement of charging of said voltage across the capacitor;

second compensation means coupled to said second sampling means for adjusting said second threshold voltage to be the second voltage modified by a voltage difference between the second voltage and said second sampled voltage; and

differential voltage setting means coupled to said second compensation means for selecting the second voltage from a plurality of different possible voltages and thereby selecting a voltage difference between the first and second voltages;

memory means coupled to said oscillator means for providing signals to said oscillator means for trimming frequency of said system clock;

microcontroller logic means having trimming data stored therein for providing said trimming data to said memory means;

said microcontroller logic means also including oscillator control means therein for selecting between use of said oscillator means internal to said microcontroller for said system clock and use of an external oscillator source for said system clock;

oscillator logic means coupled to said microcontroller logic means, to said oscillator means, and to said external oscillator source for providing, in response to receipt of a signal from said oscillator control means, said system clock to said microcontroller from one of said oscillator means and said external oscillator source;

said memory means comprising Static Random Access Memory (SRAM) having control register means for storing said trimming data and supplying said trimming data to said oscillator means; and

trimming data adjustment means within said microcontroller logic means for altering said trimming data after said trimming data has been transferred to said memory means.