Scaleable refresh display controller

• US 5,796,391 A
• Filed: 10/24/1996
• Issued: 08/18/1998
• Est. Priority Date: 10/24/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Chiu, Scott, Novis, Scott R.
• Primary Examiner(s): Hjerpe, Richard A.
• Assistant Examiner(s): Osorio, Ricardo
• Application Number:
  US08/740,050
• Time in Patent Office: 663 Days
• Field of Search: 345/204, 345/213, 345/56, 345/127, 345/128, 345/129, 345/130, 345/131, 345/132, 345/185, 345/189, 345/190, 345/200, 340/825.44, 348/524, 348/536, 348/537, 348/541
• US Class Current: 345/204
• CPC Class Codes: G09G 2330/021 Power management, e.g. power saving
• CPC Class Codes: G09G 3/20 for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
• CPC Class Codes: G09G 3/2011 by amplitude modulation
• CPC Class Codes: G09G 3/2014 by modulation of the duration of a single pulse during which the logic level remains constant
• CPC Class Codes: G09G 3/2018 by time modulation using two or more time intervals
• CPC Class Codes: G09G 3/32 semiconductive, e.g. using light-emitting diodes [LED]
• CPC Class Codes: G09G 5/008 Clock recovery

Abstract

A display controller (112) reduces the power consumed in displaying a graphics image in a portable wireless communications device (100) when a graphics image is smaller than the size of the display (118). The number of rows and columns used to display the graphics image is counted by a decoder (108) which is a microcontroller used to operate the communications device (100). The decoder (108) provides the reduced row or column count to the display controller (112), which reduces the frequencies of clocks (PIXEL CLOCK, LINE PULSE, FRAME PULSE) used for timing data transfers to the display (118). Power is reduced by operating the display (118) at a lower frequency while acceptable frame refresh rates are maintained.

Claims

1. A wireless communications device for viewing an image on a display, comprising:

a radio frequency (RF) circuit having an input coupled for receiving a RF input signal and an output;

a demodulator having an input coupled to the output of the RF circuit and having an output for providing a baseband data signal;

a decoder circuit having an input for receiving the baseband data signal for providing image data, where the decoder circuit counts a number of pixels within a line of the image data to produce a pixel count and divides a number of pixels within a line of the display by the pixel count to compute a pixel rate divisor;

a circuit for clocking the display, including

(1) a first divider having a clock input for receiving a clock signal, a data input for receiving the pixel rate divisor, and an output for providing a pixel clock for transferring the image data to the display; and

(2) a second divider having a clock input for receiving the pixel clock, a data input for receiving the pixel count, and an output for providing a line clock having a substantially constant period as a period of the pixel clock varies.

2. A clocking circuit for driving a display device, comprising:

a decoder circuit having an input for receiving a data stream and an output for providing image data, the decoder circuit counting a number of pixels within a line of the image data to produce a pixel count and dividing a number of pixels within a line of the display device by the pixel count to compute a pixel rate divisor;

a first divider having a clock input for receiving a clock signal, a data input for receiving the pixel rate divisor, and an output for providing a pixel clock for transferring the image data; and

a second divider having a clock input for receiving the pixel clock, a data input for receiving the pixel count, and an output for providing a line clock having a substantially constant period as a period of the pixel clock varies.

3. The clocking circuit of claim 2, wherein the decoder circuit counts a number of lines within a frame of the image data to produce a line count.

4. The clocking circuit of claim 3, further comprising a third divider having a clock input for receiving the line clock, a data input for receiving the line count, and an output for providing a frame clock.

5. The clocking circuit of claim 2, wherein the first divider includes:

a first latch having a first input for receiving the pixel rate divisor from the decoder circuit, and a second input coupled for receiving a first control signal to latch the pixel rate divisor at an output; and

a first binary counter having an input coupled to the output of the first latch for counting to the pixel rate divisor to produce the pixel clock.

6. The clocking circuit of claim 5, wherein the second divider comprises:

a second latch having a first input for receiving the pixel count from the decoder circuit, and a second input coupled for receiving a second control signal to latch the pixel count at an output; and

a second binary counter having an input coupled to the output of the second latch for counting to the pixel count to produce the line clock.

7. The clocking circuit of claim 4, wherein the third divider comprises:

a third latch having a first input for receiving the line count from the decoder circuit, and a second input coupled for receiving a third control signal to latch the line count at an output; and

a third binary counter having an input coupled to the output of the third latch for counting to the line count to produce the frame clock.

8. The clocking circuit of claim 7, further comprising:

a fourth latch having a first input coupled for receiving a starting address from the decoder circuit and a second input coupled for receiving a fourth control signal to latch the starting address at an output; and

an address counter having a data input coupled to the output of the fourth latch, a clock input coupled for receiving the pixel clock and an output for providing a memory address for storing the image data.

9. The clocking circuit of claim 8, further comprising an address decoder having an input coupled to the decoder circuit for receiving control data, and decoding the control data to provide the first through fourth control signals at first through fourth outputs, respectively.

10. A method of clocking a display, comprising the steps of:

counting a number of pixels within a line of the image data to produce a pixel count;

dividing a number of pixels within a line of the display by the pixel count to compute a pixel rate divisor;

counting a system clock to the pixel rate divisor to produce a pixel clock for transferring the image data; and

counting the pixel clock to the pixel count to produce a line clock having a substantially constant period as a period of the pixel clock varies.

11. The method of claim 10, further comprising the step of counting a number of lines within a frame of the image data to produce a line count.

12. The method of claim 11, further comprising the step of counting the line clock to the line count to produce a frame clock.

13. The method of claim 12, wherein the step of counting the system clock includes the step of latching the pixel rate divisor.

14. The method of claim 13, wherein the step of counting the pixel clock includes the step of latching the pixel count, and the step of counting the line clock includes the step of latching the line count.