Extended symmetrical multiprocessor address mapping

• US 5,796,605 A
• Filed: 07/02/1996
• Issued: 08/18/1998
• Est. Priority Date: 07/02/1996
• Status: Expired due to Fees

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Hagersten, Erik E.
• Primary Examiner(s): Trammell, James P.
• Assistant Examiner(s): Bui, Bryan
• Application Number:
  US08/675,361
• Time in Patent Office: 777 Days
• Field of Search: 364/134, 364/243, 364/243.41, 364/228.1, 364/230, 364/243.4, 395/427, 395/444, 395/445, 395/468, 395/472, 395/480, 395/497.4, 395/200.08, 395/200.09, 395/497.03, 395/200.83, 395/200.78, 395/200.79, 711/141, 711/145, 711/143, 711/5
• US Class Current: 700/5
• CPC Class Codes: G06F 15/173 using an interconnection network, e.g. matrix, shuffle, pyramid, star, snowflake

Abstract

A technique for system memory space address mapping in a multiprocessor computer system is provided. The disclosed mapping architecture may be applied to a multiprocessor computer system having multiple processing nodes (SMP nodes), where each processing node may include multiple processors. The system memory address space is split into different regions such that each of the n SMP nodes is assigned 1/n of the total address space. Cache coherency state information is stored for the memory in each SMP node. Memory regions may further be assigned to operate in one of three modes: normal, migratory, or replicate. When operating in normal mode, transaction to an address space assigned to a particular node are tried only locally in that node first. Transactions may be sent globally to other nodes if an improper cache coherency state is returned or if the address corresponds to a memory region assigned to another node. In migratory mode transactions are always sent globally. And in replicate mode duplicate copies of the replicate memory region are assigned to each SMP node so that transactions are always tried locally first, and only sent globally if an improper cache coherency state is returned.

Claims

1. A memory mapping method for the system memory address space of a multiprocessor computer system having a plurality of processing nodes, each processing node having a plurality of bus devices, the method comprising:

dividing the system memory address space into multiple regions, wherein the number of regions equals the number of processing nodes in said microprocessor computer system, and wherein the amount of system memory address space encompassed by each one of said regions is inversely proportional to the number of said processing nodes;

assigning a different one of said regions to each one of said processing nodes, wherein each processing node has a local address space corresponding its assigned one of said regions;

attempting a local address space transaction in the processing node to which the corresponding one of said regions is assigned, wherein said local address space transaction is broadcast to each bus device in the corresponding node without broadcasting said local address space transaction to the other processing nodes in said multiprocessor computer system;

checking memory access rights for said local address space transaction; and

reissuing said local address space transaction to all of said processing nodes in said multiprocessor computer system if said checking determines improper access rights.

2. The memory mapping method as recited in claim 1, further comprising:

mapping a portion of said local address space for each processing node to physical memory located in that node; and

maintaining memory coherency state information for said portion of said local address space for each processing node.

3. The memory mapping method as recited in claim 2, wherein said checking comprises retrieving said memory coherency state information.

4. The memory mapping method as recited in claim 2, wherein said maintaining comprises:

dividing said physical memory into coherency units; and

maintaining said coherency state information for each coherency unit.

5. The memory mapping method as recited in claim 3, wherein said checking further comprises determining if said access rights are improper according to a cache coherency protocol.

6. A memory mapping method for the system memory address space of a multiprocessor computer system having a plurality of processing nodes having memory, the method comprising:

dividing the system memory address space into multiple operating regions;

assigning a particular operating mode to each operating region, wherein said particular operating mode is either normal mode, migratory mode, or replicate mode;

further dividing the system memory address space into multiple mapping regions, wherein the number of mapping regions equals the number of processing nodes in said microprocessor computer system, and wherein the amount of system memory address space encompassed by each one of said mapping regions is inversely proportional to the number of said processing nodes;

assigning a different one of said mapping regions to each one of said processing nodes, wherein each processing node has a local address space corresponding its assigned one of said mapping regions;

attempting a local address space transaction in the node to which the corresponding one of said mapping regions is assigned, wherein;

said local address space transaction is attempted without broadcasting said local address space transaction to the other processing nodes in said multiprocessor computer system if said local address space transaction corresponds an operating region assigned to normal mode or replicate mode;

said local address space transaction broadcast to all processing nodes in said multiprocessor computer system if said local address space transaction corresponds an operating region assigned to migratory mode.

7. The memory mapping method as recited in claim 6, further comprising:

checking memory access rights for said local address space transaction if said local address space transaction corresponds an operating region assigned to normal mode or replicate mode; and

reissuing said local address space transaction to all of said processing nodes in said multiprocessor computer system if said checking determines improper access rights.

8. The memory mapping method as recited in claim 6, further comprising assigning to each processing node an operating region assigned to replicate node, wherein said operating region assigned to replicate mode is duplicated in each processing node.

9. The memory mapping method as recited in claim 6, further comprising maintaining a freelist indicating portions of said mapping regions available to be assigned to an operating region assigned to said replicate mode.

10. A multiprocessor computer system, comprising:

a plurality of processing nodes, wherein each processing node comprises a plurality of bus devices coupled by a lower-level bus structure;

an upper level bus structure configured to interconnect said plurality of processing nodes;

system memory comprising memory devices on each processing node and having a system memory address space divided into a region for each processing node; and

wherein each processing node is configured to broadcast a system memory address space transaction to each bus device on that node and not broadcast the transaction to the other processing nodes if the transaction is addressed to the region corresponding to that node.

11. The multiprocessor computer system as recited in claim 10, wherein each processing node is configured to broadcast a system memory address space transaction to each of the other processing nodes if the transaction is not addressed to the region corresponding to that node.

12. The multiprocessor computer system as recited in claim 10, wherein each processing node further comprising memory locations for storing coherency information for the portion of system memory on that node.

13. The multiprocessor computer system as recited in claim 12, wherein each said processing node is further configured to check said coherency information for a transaction originating on that node and addressed to the region corresponding to that node and to broadcast the transaction to the other processing nodes if the coherency information for the transaction indicates improper access rights.

14. A multiprocessor computer system, comprising:

a plurality of processing nodes;

an upper-level interconnect structure configured to couple said processing nodes;

system memory partitioned among said processing node and addressable through a system memory address space;

wherein a first portion of said system memory address space is accessed in a normal mode and a second portion of said system memory address space is accessed in a migratory mode;

wherein in said normal mode, transactions to system memory address space corresponding to a particular node are attempted without broadcasting the transaction to the other processing nodes; and

wherein in said migratory mode, transactions to system memory address space corresponding to a particular node are broadcast to all processing nodes.

15. The multiprocessor computer system as recited in claim 14, wherein a third portion of said system memory address space is accessed in a replicate mode, wherein in said replicate mode, transactions to system memory address space corresponding to a particular node are attempted without broadcasting the transaction to the other processing nodes, wherein the portion of said system memory address space accessed in said replicate mode is duplicated in each processing node.

16. The multiprocessor computer system as recited in claim 15, further comprising a freelist in said system memory configured to indicate the portions of said system memory available to be assigned to the replicate mode.

17. The multiprocessor computer system as recited in claim 14, wherein each processing node further comprising memory locations for storing coherency information for the portion of system memory on that node.

18. The multiprocessor computer system as recited in claim 17, wherein each said processing node is further configured to check said coherency information for a normal mode transaction originating on that node and addressed to a portion of system memory address space corresponding to that node and to broadcast the transaction to the other processing nodes if the coherency information for the transaction indicates improper access rights.