Physical design automation system and process for designing integrated circuit chip using simulated annealing with "chessboard and jiggle" optimization

• US 5,796,625 A
• Filed: 03/01/1996
• Issued: 08/18/1998
• Est. Priority Date: 03/01/1996
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: LSI Logic Corporation (Broadcom, Inc.)
• Inventors: Scepanovic, Ranko, Andreev, Alexander E., Koford, James S., Pavisic, Ivan
• Primary Examiner(s): Louis-Jacques, Jacques H.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US08/609,359
• Time in Patent Office: 900 Days
• Field of Search: 364/489, 364/490, 364/491, 364/148, 395/500, 395/821, 395/800, 395/840
• US Class Current: 716/123
• CPC Class Codes: G06F 30/392 Floor-planning or layout, e.g. partitioning or placement

Abstract

A cell placement for an integrated circuit chip is divided into two "chessboard" patterns or "jiggles". Each pattern resembles a chessboard in that it consists of alternating regions of different types or "colors" such that no region of a given color has an edge common with another region of the same color. The jiggles are offset relative to each other such that the regions of one jiggle partially overlap at least two regions of the other jiggle. Simulated annealing is performed sequentially for each color of each jiggle. During each operation, a plurality of parallel processors operate on the regions simultaneously using a previous copy of the entire chip, with one processor being assigned to one or more regions. At the end of each operation, the copy of the chip is updated. The chessboard patterns eliminate unproductive cell moves resulting from adjacent regions having a common edge. The jiggles enable cells to move to their optimal positions from their initial region to any other region on the chip. The regions can have rectangular, triangular or hexagonal shapes. An initial temperature for the actual simulated annealing operation is determined by performing simulated annealing without cell swaps with different temperature, and selecting the temperature at which a cost function such as total wirelength does not significantly change.

Claims

1. A method of providing an initial temperature in a simulated annealing process, comprising the steps of:

(a) providing a placement of cells on the chip;

(b) performing simulated annealing on the cells using a current temperature without exchanging cell positions;

(c) computing a current cost function for the placement;

(d) changing said current temperature in accordance with said cost function; and

(e) repeating steps (b) to (d) until said current cost function satisfies a predetermined criterion, wherein said current temperature is used as said initial temperature for said simulated annealing process when said predetermined criterion is satisfied.

2. A method as in claim 1, in which said predetermined criterion is such that a change in said cost function is less than a predetermined value.

3. A method as in claim 1, further comprising the step, performed between steps (a) and (b), of:

(f) dividing the chip into a set of first regions, and a set of second regions that spatially alternate with the first regions;

in which step (b) comprises the substeps of;

(b1) performing simulated annealing on cells in the first regions; and

(b2) performing simulated annealing on cells in the second regions.

4. A method as in claim 3, in which the first regions do not have edges that are common to edges of other first regions, and the second regions do not have edges that are common to edges of other second regions.

5. A method as in claim 3, in which:

step (f) further comprises dividing the chip into a set of third regions, and a set of fourth regions that spatially alternate with the third regions, such that the third regions overlap the first and second regions, and the fourth regions also overlap the first and second regions; and

step (b) further comprises the substeps of;

(b3) performing simulated annealing on cells in the third regions; and

(b4) performing simulated annealing on cells in the fourth regions.

6. A method as in claim 3, in which steps (b1) and (b2) comprise performing simulated annealing on pluralities of the first and second regions simultaneously using pluralities of parallel processors respectively.

7. A method as in claim 6, further comprising the step of:

(g) assigning approximately equal total areas of cells to the parallel processors respectively.

8. A method as in claim 6, further comprising the step of:

(g) assigning approximately equal numbers of regions to the parallel processors respectively.

9. A method as in claim 6, in which:

steps (b1) and (b2) comprise performing simulated annealing based on a copy of the entire chip; and

the method further comprises the steps of;

(g) after performing step (b1), updating said copy; and

(h) after performing step (b2), updating said copy.

10. A method of designing an integrated circuit chip dependent on claim 1, comprising the steps of:

providing an initial temperature in accordance with the steps (a) through (e) of the method of claim 1;

(f) performing simulated annealing on the cells including exchanging cell positions;

(g) computing a new temperature in accordance with a number of accepted swaps; and

(h) repeating steps (f) and (g) until a difference between consecutive values of said new temperature computed in step (g) satisfies a predetermined criterion.

11. A programmed digital computer as in claim 1, in which said predetermined criterion is such that a change in said cost function is less than a predetermined value.

12. A programmed digital computer as in claim 1, in which the processing means, memory means and program operating in combination further perform the step, between steps (a) and (b), of:

(f) dividing the chip into a set of first regions, and a set of second regions that spatially alternate with the first regions;

in which step (b) comprises the substeps of;

(b1) performing simulated annealing on cells in the first regions; and

(b2) performing simulated annealing on cells in the second regions.

13. A programmed digital computer as in claim 12, in which the first regions do not have edges that are common to edges of other first regions, and the second regions do not have edges that are common to edges of other second regions.

14. A programmed digital computer as in claim 12, in which:

step (f) further comprises dividing the chip into a set of third regions, and a set of fourth regions that spatially alternate with the third regions, such that the third regions overlap the first and second regions, and the fourth regions also overlap the first and second regions; and

step (b) further comprises the substeps of;

(b3) performing simulated annealing on cells in the third regions; and

(b4) performing simulated annealing on cells in the fourth regions.

15. A programmed digital computer as in claim 12, in which:

the processing means comprises a plurality of parallel processors; and

steps (b1) and (b2) comprise performing simulated annealing on pluralities of the first and second regions simultaneously using the parallel processors respectively.

16. A programmed digital computer as in claim 15, in which the processing means, memory means and program operating in combination further perform the step of:

(g) assigning approximately equal total areas of cells to the parallel processors respectively.

17. A programmed digital computer as in claim 15, in which the processing means, memory means and program operating in combination further perform the step of:

(g) assigning approximately equal numbers of regions to the parallel processors respectively.

18. A programmed digital computer as in claim 15, in which:

steps (b1) and (b2) comprise performing simulated annealing based on a copy of the entire chip; and

the processing means, memory means and program operating in combination further perform the steps of;

(g) after performing step (b1), updating said copy; and

(h) after performing step (b2), updating said copy.

19. A method as in claim 1, wherein said placement of cells of step (a) results in an original cost function, and said predetermined criterion is defined as when the current cost function is substantially equal to the original cost function.

20. A method as in claim 19, wherein said changing said current temperature of step (d) includes reducing the current temperature if the current cost function is higher than the original cost function.

21. A method as in claim 20, wherein said changing said current temperature of step (d) includes increasing the current temperature if the current cost function is lower than the original cost function.

22. A programmed digital computer as in claim 1, wherein said placement of cells of step (a) results in an original cost function, and said predetermined criterion is defined as when the current cost function is substantially equal to the original cost function.

23. A programmed digital computer as in claim 22, wherein said changing said current temperature of step (d) includes reducing the current temperature if the current cost function is higher than the original cost function.

24. A programmed digital computer as in claim 23, wherein said changing said current temperature of step (d) includes increasing the current temperature if the current cost function is lower than the original cost function.

25. A programmed digital computer for designing an integrated circuit chip, comprising:

memory means for storing a program including instructions and data; and

processing means for executing the program;

the processing means, memory means and program operating in combination for performing the steps of;

(a) providing a placement of cells on the chip;

(b) performing simulated annealing on the cells using a current temperature without exchanging cell positions;

(c) computing a current cost function for the placement;

(d) changing said current temperature in accordance with said cost function; and

(e) repeating steps (b) to (d) until said current cost function satisfies a predetermined criterion, wherein the current temperature is used as an initial temperature for a simulated annealing process when said predetermined criterion is satisfied.

26. A programmed digital computer as in claim 25, in which the processing means, memory means and program operating in combination further perform the step, after step (e), of:

(f) performing simulated annealing on the cells including exchanging cell positions;

(g) computing a new temperature in accordance with a number of accepted swaps; and

(h) repeating steps (f) and (g) until a difference between consecutive values of said new temperature computed in step (g) satisfies a predetermined criterion.

27. A method of designing an integrated circuit chip, comprising the steps of:

(a) providing a placement of cells on the chip;

(b) dividing the chip into a set of first, second, third and fourth regions, wherein the second regions spatially alternate with the first regions, and wherein the fourth regions spatially alternate with the third regions, such that the third regions overlap the first and second regions, and the fourth regions also overlap the first and second regions;

(c) performing simulated annealing on cells in the first, second, third and fourth regions using an initial temperature without exchanging cell positions;

(d) computing a cost function for the placement;

(e) computing a new temperature in accordance with said cost function; and

(f) repeating steps (c) to (e) until said cost function satisfies a predetermined criterion.

28. A programmed digital computer for designing an integrated circuit chip, comprising:

memory means for storing a program including instructions and data; and

processing means for executing the program, wherein the processing means, memory means and program operate in combination for performing the steps of;

(a) providing a placement of cells on the chip;

(b) dividing the chip into a set of first, second, third and fourth regions, wherein the second regions spatially alternate with the first regions, and wherein the fourth regions spatially alternate with the third regions, such that the third regions overlap the first and second regions, and the fourth regions also overlap the first and second regions;

(c) performing simulated annealing on cells in the first, second, third and fourth regions using an initial temperature without exchanging cell positions;

(d) computing a cost function for the placement;

(e) computing a new temperature in accordance with said cost function; and

(f) repeating steps (c) to (e) until said cost function satisfies a predetermined criterion.