Methods, apparatus and computer program products for synthesizing integrated circuits with electrostatic discharge capability and connecting ground rules faults therein

• US 5,796,638 A
• Filed: 06/24/1996
• Issued: 08/18/1998
• Est. Priority Date: 06/24/1996
• Status: Expired due to Term

• Current Assignee: Board of Trustees of The University of Illinois, Avago Technologies General IP PTE Limited (Broadcom, Inc.), Texas Instruments, Inc.
• Original Assignee: Board of Trustees of The University of Illinois, Hewlett-Packard Company (HP Inc.), Texas Instruments, Inc.
• Inventors: Diaz, Carlos Hernando, Kang, Sung-Mo Steve, Duvvury, Charvaka, Ramaswamy, Sridhar
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): PHAN, THAI Q
• Application Number:
  US08/668,856
• Time in Patent Office: 785 Days
• Field of Search: 364/488, 364/489, 364/578, 364/483, 257/355, 257/358, 257/370, 437/51, 437/59, 437/34
• US Class Current: 716/112
• CPC Class Codes: G06F 30/39 Circuit design at the physical level physical level design for reconfigurable circuits G06F30/347
• CPC Class Codes: H01L 27/0248 for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection

Abstract

A method, apparatus and computer program product for synthesizing and correcting ESD and EOS ground rules faults in integrated circuits generates a representation of a first functional circuit element (e.g., logic gate) connected to a representation of a first input/output (I/O) pad, via a representation of a first electrical path, and generates a representation of a first ESD circuit element connected to the representation of the first input/output pad via a representation of a second electrical path which may overlap a portion of the first electrical path. First and second sheet resistances (or quantities related thereto) of the first and second electrical paths, respectively, are determined and a length and/or width of the representation of at least one of the first and second electrical paths is adjusted if the first sheet resistance is greater than the second sheet resistance, so that the first sheet resistance is less than the second sheet resistance. Corners in representations of adjacent power rails are also detected, where these representations have opposing edges separated by a minimum rail spacing, and a position of at least one of the power rails relative to the other is adjusted so that the opposing edges are separated by a spacing which is no less than about two times the minimum rail spacing.

Claims

1. A method of synthesizing a computer readable representation of an integrated circuit with electrostatic discharge protection capability, comprising the steps of:

generating a computer readable representation of an integrated circuit containing a representation of a first functional circuit element connected to a representation of a first input/output pad, via a representation of a first electrical path, and a representation of a first electrostatic discharge protection circuit element connected to the representation of the first input/output pad, via a representation of a second electrical path;

determining a quantity relating to a first sheet resistance of the representation of the first electrical path and determining a quantity relating to a second sheet resistance of the representation of the second electrical path; and

adjusting a length and/or width of the representation of at least one of the first and second electrical paths to improve the electrostatic discharge capability of the integrated circuit, if the first sheet resistance is greater than the second sheet resistance; and

wherein the first electrostatic discharge protection circuit element is characterized by a trigger voltage (V_trigPD), an on-resistance (R_on) and a maximum ESD current I_ESD ;

wherein the first functional circuit element is characterized by a trigger voltage (V_trigF); and

wherein V_trigPD +R_on I_ESD <

V_trigF.

2. The method of claim 1, further comprising the step of updating the computer readable representation of the integrated circuit with the adjusted length and/or width of the representation of at least one of the first and second electrical paths.

3. The method of claim 2, further comprising the step of visually displaying a schematic of the generated computer readable representation of the integrated circuit in at least two dimensions.

4. The method of claim 3, further comprising the step of repositioning the first electrostatic discharge protection circuit element and/or the second electrical path relative to the first input/output pad, in the displayed schematic, if the first sheet resistance is greater than the second sheet resistance.

5. An apparatus for synthesizing a computer readable representation of an integrated circuit with electrostatic discharge protection capability, comprising:

means for generating a computer readable representation of an integrated circuit containing a representation of a first functional circuit element connected to a representation of a first input/output pad, via a representation of a first electrical path, and a representation of a first electrostatic discharge protection circuit element connected to the representation of the first input/output pad, via a representation of a second electrical path, said first electrostatic discharge protection circuit element characterized by a trigger voltage (V_trigPD), an on-resistance (R_on) and a maximum ESD current I_ESD and said first functional circuit element characterized by a trigger voltage (V_trigF); and

wherein V_trigPD +R_on I_ESD <

V_trigF ;

means, responsive to said generating means, for determining a quantity relating to a first sheet resistance of the representation of the first electrical path and determining a quantity relating to a second sheet resistance of the representation of the second electrical path; and

means, responsive to said quantity determining means, for adjusting a length and/or width of the representation of at least one of the first and second electrical paths to improve the electrostatic discharge capability of the integrated circuit, if the first sheet resistance is greater than the second sheet resistance.