Integrated circuit chip with a wide I/O memory array and redundant data lines

• US 5,796,662 A
• Filed: 11/26/1996
• Issued: 08/18/1998
• Est. Priority Date: 11/26/1996
• Status: Expired due to Term

• Current Assignee: International Business Machines Corporation
• Original Assignee: International Business Machines Corporation
• Inventors: Barth, John Edward Jr., Kalter, Howard Leo
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): TRAN, MICHAEL THANH
• Application Number:
  US08/756,614
• Time in Patent Office: 630 Days
• Field of Search: 365/200, 365/189.08
• US Class Current: 365/200
• CPC Class Codes: G11C 29/848 by adjacent switching

Abstract

An integrated circuit chip with RAM, a RAM macro or bit slice data logic and at least one spare array element or spare slice element and the redundancy scheme therefor. The chip includes a wide data path with a plurality of interchangeable elements such as bit slice elements or memory element and at least one more element than the number of bits in the wide data path; selection logic for deselecting defective data elements; and, switches for selectively coupling each bit of the wide I/O data path to one element or to an element adjacent the one element responsive to the selection means. The integrated circuit chip may further include drive means for selectively driving data from the switches to the element or, otherwise, passing data from the elements to the switches. The switches preferably are three-way switches, such as three CMOS pass gates.

Claims

1. An integrated circuit chip having a data path at least 4 bytes wide, said integrated circuit chip comprising:

a plurality of arrays, each of said arrays including a plurality of interchangeable elements, said plurality of interchangeable elements being at least one more than the number of bits in said data path and connected to corresponding interchangeable elements of other of said plurality of memory arrays;

selection means for deselecting defective elements;

programming means in each said array for providing said selection means with a defective element location within said array; and

switching means for selectively coupling each bit of said data path to a correspond element or, responsive to said selection means, to a corresponding adjacent element.

2. The integrated circuit chip of claim 1 wherein said array is a memory array and said elements are memory elements.

3. The integrated circuit chip of claim 2 wherein said memory elements are memory array columns.

4. The integrated circuit chip of claim 3 wherein said selection means comprises:

a plurality of partial decoders responsive to a defective column address; and

,

a plurality of final decoders for driving a shift column signal to said defective column signal to said defective column and at each column to one side of said defective column.

5. The integrated circuit chip of claim 1 wherein said switching means is a plurality of three-way switches.

6. The integrated circuit chip of claim 5 wherein each of said three-way switches is three CMOS pass gates.

7. The integrated circuit chip of claim 1 further comprising:

drive means for selectively driving data from said switching means to said array or for passing data from said data path to said switching means.

8. An integrated circuit chip having a data path at least 8 bytes wide and including a RAM, said RAM comprising:

a plurality of memory arrays, each said memory array having a plurality of interchangeable columns, said plurality of interchangeable columns being at least one more than said data path and connected to corresponding columns of other of said plurality of memory arrays;

selection means for deselecting defective columns, said selection means comprising;

a plurality of partial decoders responsive to at least one defective column address, and,

a plurality of final decoders for driving responsive to said partial decoders, a shift column signal to said defective column and to each column to one side of each defective column;

programming means in each said memory array for providing said selection means with defective column locations within said array; and

switching means for selectively coupling each bit of said data path to a corresponding column or, responsive to said shift column signals, to a corresponding adjacent column.

9. The integrated circuit chip of claim 8 further comprising:

drive means for selectively driving data from said switching means to said data path or for passing data from said data path to said switching means.

10. The integrated circuit chip of claim 9 wherein said switching means is a plurality of three-way switches.

11. The integrated circuit chip of claim 10 wherein each of said plurality of three-way switches is three CMOS pass gates.

12. An integrated circuit chip having a data path at least 8 bytes wide and including a RAM, said RAM including a plurality of memory arrays and comprising:

a plurality of interchangeable columns in each said memory array, said plurality of interchangeable columns being at least one more than said data path and connected to corresponding columns of other of said plurality of memory arrays;

selection means for deselecting defective columns, said selection means comprising;

three partial decoders responsive to at least one defective column address, and

a plurality of final decoders for driving, responsive to said partial decoders, a shift column signal to said defective column and to each column to one side of each said defective column, such that columns to one side of a first defective column are shifted one column and columns to the same side of a second defective column are shifted two columns;

programming means for providing said selection means with defective column locations within said each memory array;

switching means comprising a plurality of three-way switches, said switching means for selectively coupling each bit of said data path to a corresponding column or, responsive to said selection means, to a corresponding adjacent column; and

drive means for selectively driving data from said switching means to said data path or for passing data from said data path to said switching means.

13. The integrated circuit chip of claim 12 wherein each of said three-way switches is three CMOS pass gates.