Code sequence generator in a CDMA modem

• US 5,796,776 A
• Filed: 06/27/1996
• Issued: 08/18/1998
• Est. Priority Date: 06/30/1995
• Status: Expired due to Term

• Current Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Original Assignee: Interdigital Technology Corporation (InterDigital, Inc.)
• Inventors: Ozluturk, Fatih, Lomp, Gary, Silverberg, Avi
• Primary Examiner(s): Chin, Stephen
• Assistant Examiner(s): Le, Amanda T.
• Application Number:
  US08/669,769
• Time in Patent Office: 782 Days
• Field of Search: 375/200, 375/205, 375/206, 375/367, 364/717.01, 364/717.03, 364/717.04, 364/717.05, 364/717.07, 370/320, 370/335, 370/342, 370/575, 380/44, 380/46, 380/47
• US Class Current: 375/222
• CPC Class Codes: G06F 13/374 using a self-select method with individual priority code comparator
• CPC Class Codes: H03H 17/0226 comprising look-up tables
• CPC Class Codes: H03H 17/06 Non-recursive filters
• CPC Class Codes: H04B 1/707 using direct sequence modulation
• CPC Class Codes: H04B 1/7075 with code phase acquisition
• CPC Class Codes: H04B 1/70753 Partial phase search
• CPC Class Codes: H04B 1/70754 Setting of search window, i.e. range of code offsets to be searched H04B1/70758 takes precedence
• CPC Class Codes: H04B 1/70755 Setting of lock conditions, e.g. threshold
• CPC Class Codes: H04B 1/70758 Multimode search, i.e. using multiple search strategies
• CPC Class Codes: H04B 1/7077 Multi-step acquisition, e.g. multi-dwell, coarse-fine or validation
• CPC Class Codes: H04B 1/708 Parallel implementation
• CPC Class Codes: H04B 1/7085 using a code tracking loop, e.g. a delay-locked loop
• CPC Class Codes: H04B 1/709 Correlator structure
• CPC Class Codes: H04B 1/7093 Matched filter type
• CPC Class Codes: H04B 1/711 the interference being multi-path interference
• CPC Class Codes: H04B 1/7115 Constructive combining of multi-path signals, i.e. RAKE receivers
• CPC Class Codes: H04B 1/712 Weighting of fingers for combining, e.g. amplitude control or phase rotation using an inner loop
• CPC Class Codes: H04B 2201/70701 featuring pilot assisted reception
• CPC Class Codes: H04B 2201/70702 Intercell-related aspects
• CPC Class Codes: H04B 2201/70703 using multiple or variable rates
• CPC Class Codes: H04B 2201/70707 : Efficiency-related aspects
• CPC Class Codes: H04B 2201/7071 : with dynamic control of receiver resources
• CPC Class Codes: H04B 7/2628 : using code-division multiple access [CDMA] or spread spectrum multiple access [SSMA] H04B7/2618 takes precedence
• CPC Class Codes: H04B 7/2637 : for logical channel control
• CPC Class Codes: H04B 7/264 : for data rate control
• CPC Class Codes: H04J 13/00 : Code division multiplex systems for frequency hopping H04B1/713
• CPC Class Codes: H04J 13/004 : Orthogonal
• CPC Class Codes: H04J 13/0048 : Walsh
• CPC Class Codes: H04J 13/0077 : Multicode, e.g. multiple codes assigned to one user
• CPC Class Codes: H04J 13/10 : Code generation
• CPC Class Codes: H04J 13/107 : by concatenation
• CPC Class Codes: H04J 13/12 : Generation of orthogonal codes
• CPC Class Codes: H04J 13/16 : Code allocation
• CPC Class Codes: H04J 2013/0037 : Multilevel codes
• CPC Class Codes: H04L 1/0001 : Systems modifying transmission characteristics according to link quality, e.g. power backoff adaptive data allocation for multicarrier modulation H04L5/0044; controlling transmission power for radio systems H04W52/04
• CPC Class Codes: H04L 1/004 : by using forward error control H04L1/0618 takes precedence; coding, decoding or code conversion, for error detection or correction H03M13/00
• CPC Class Codes: H04L 1/0042 : Encoding specially adapted to other signal generation operation, e.g. in order to reduce transmit distortions, jitter, or to improve signal shape H04L1/0067 takes precedence
• CPC Class Codes: H04L 1/0047 : Decoding adapted to other signal detection operation in conjunction with sequence estimation or equalization H04L25/03286
• CPC Class Codes: H04L 1/0054 : Maximum-likelihood or sequential decoding, e.g. Viterbi, Fano, ZJ algorithms
• CPC Class Codes: H04L 1/0059 : Convolutional codes
• CPC Class Codes: H04L 2027/003 : at baseband only
• CPC Class Codes: H04L 2027/0053 : Closed loops
• CPC Class Codes: H04L 25/0212 : of impulse response
• CPC Class Codes: H04L 27/206 : using a pair of orthogonal carriers, e.g. quadrature carriers
• CPC Class Codes: H04L 27/2332 : using a non-coherent carrier
• CPC Class Codes: H04L 5/1446 : of transmission speed
• CPC Class Codes: H04N 1/00912 : Arrangements for controlling a still picture apparatus or components thereof not otherwise provided for
• CPC Class Codes: H04N 1/3333 : during transmission, input or output of the picture signal; within a single document or page
• CPC Class Codes: H04N 2201/3335 : Speed or rate
• CPC Class Codes: H04W 52/04 : TPC
• CPC Class Codes: H04W 52/08 : Closed loop power control
• CPC Class Codes: H04W 52/143 : Downlink power control
• CPC Class Codes: H04W 52/146 : Uplink power control
• CPC Class Codes: H04W 52/24 : using SIR [Signal to Interference Ratio] or other wireless path parameters
• CPC Class Codes: H04W 52/241 : taking into account channel quality metrics, e.g. SIR, SNR, CIR, Eb/lo
• CPC Class Codes: H04W 52/245 : taking into account received signal strength
• CPC Class Codes: H04W 52/247 : where the output power of a terminal is based on a path parameter sent by another terminal
• CPC Class Codes: H04W 52/26 : using transmission rate or quality of service QoS [Quality of Service]
• CPC Class Codes: H04W 52/262 : taking into account adaptive modulation and coding [AMC] scheme AMC per se H04L1/0001
• CPC Class Codes: H04W 52/322 : Power control of broadcast channels
• CPC Class Codes: H04W 52/325 : Power control of control or pilot channels
• CPC Class Codes: H04W 52/343 : taking into account loading or congestion level
• CPC Class Codes: H04W 52/346 : distributing total power among users or channels
• CPC Class Codes: H04W 52/36 : with a discrete range or set of values, e.g. step size, ramping or offsets
• CPC Class Codes: H04W 52/367 : Power values between minimum and maximum limits, e.g. dynamic range
• CPC Class Codes: H04W 52/44 : in connection with interruption of transmission
• CPC Class Codes: H04W 52/50 : at the moment of starting communication in a multiple access environment
• CPC Class Codes: H04W 52/52 : using AGC [Automatic Gain Control] circuits or amplifiers
• CPC Class Codes: H04W 52/54 : Signalisation aspects of the TPC commands, e.g. frame structure
• CPC Class Codes: H04W 52/60 : using different transmission rates for TPC commands
• CPC Class Codes: Y02D 10/00 : Energy efficient computing, e.g. low power processors, power management or thermal management

Abstract

A CDMA modem includes a modem transmitter having: a code generator which provides an associated pilot code signal and which generates a plurality of message code signals; a spreading circuit which produces a spread-spectrum message signal by combining each of the information signals with a respective one of the message code signals; and a global pilot code generator that provides a global pilot code signal to which the message code signals are synchronized. The CDMA modem also includes a modem receiver having an associated pilot code generator and a group of associated pilot code correlators for correlating code-phase delayed versions of the associated pilot signal with a receive CDM signal to produce a despread associated pilot signal. The code phase of the associated pilot signal is changed responsive to an acquisition signal value until a pilot signal is received. The associated pilot code tracking logic adjusts the associated pilot code signal in phase responsive to the acquisition signal so that the signal power level of the despread associated pilot code signal is maximized. Finally, the CDMA modem receiver includes a group of message signal acquisition circuits, each including a plurality of receive message signal correlators which correlate respective local received message code signal to the CDM signal to produce a respective despread received message signal.

Claims

1. A code sequence generator apparatus which generates a plurality of spreading code sequences including a master spreading code sequence, the plurality of spreading code sequences having relatively low mutual cross correlation, and having a predetermined mutual code phase relationship, said code sequence generator apparatus comprising:

a clock generator means for generating a clock signal

a linear feedback shift register (LFSR), responsive to the clock signal and having a plurality of stages including a first stage and a last stage, each stage defining a respective tap, each tap producing a tap signal;

wherein a predetermined group of the tap signals including the tap signal of the last stage are applied to logic circuitry which combines the tap signals to produce a feedback spreading-code signal, said feedback spreading-code signal being applied as an input signal to the first stage of the LFSR;

first memory means for storing a plurality of spreading-code seeds, each spreading-code seed comprising a set of spreading-code sequence bit values, and said first memory being connected to the LFSR and being responsive to a load signal for transferring each one of a predetermined set of the spreading-code sequence bit values of a selected one of the plurality of spreading-code seed into a respective one of the shift register stages of the LSFR;

code generator controller means for selecting one of the plurality of spreading-code seeds to determine the plurality of spreading code sequences and for providing the load signal indicating said one spreading-code seed;

wherein said LSFR is responsive to the clock signal to sequentially transfer each respective tap signal from one stage to the next stage, from the first stage to the last stage and for transferring the feedback spreading-code value to the first stage, and each successive one of the tap values of the last stage defines the master spreading code sequence

second memory means being responsive to the clock signal for providing a repetitive even code sequence, said even code sequence having relatively low cross correlation with the master spreading sequence and having an even number of chip spreading values;

a plurality of cascade connected feedforward means, coupled to receive the master spreading code sequence, for providing a plurality of code sequences, each code sequence being a distinct spreading code sequence of said plurality of spreading code sequences, said feedforward means being responsive to the clock signal, to provide a plurality of spreading code sequences; and

a plurality code sequence combining means, each code sequence combining means for combining respective spreading code sequence with said even code sequence to produce a plurality of relatively long spreading code.

2. The code sequence generator apparatus of claim 1, wherein the plurality of cascade connected feedforward means includes:

receiving means for receiving the master spreading sequence;

a feedforward circuit having a plurality of cascade connected feedforward logic sections, each logic section defining a tap which provides one of the plurality of spreading code sequences, including a first feedforward logic section and a last feedforward logic section and connected sequentially from the first feedforward logic section to the last feedforward logic section, each feedforward logic section comprising a single delay element having an input terminal which receives and input signal and an output terminal which provides an output signal, and logic combining means for logically combining the input signal with the output signal to produce the respective spreading code sequence.

3. The code sequence generator claim 2, wherein the code sequence combining means comprises an EXCLUSIVE-OR logic circuit.

4. The code sequence generator apparatus of claim 2, wherein the logic combining means comprises an EXCLUSIVE-OR logic circuit for performing modulo-2 addition.