Data transferring circuit which aligns clock and data
First Claim
1. A data transferring circuit for maintaining alignment between clock and data, said circuit comprising:
- input means for receiving first data at a data rate;
a clock source configured to provide a reference clock which oscillates at a frequency less than said data rate, said clock source being configured so that said reference clock oscillates at a frequency of approximately one half said data rate;
output means for presenting second data at substantially said data rate;
a data processor for transforming said first data and said reference clock into said second data and a second reference clock, respectively; and
a clock regenerator, coupled to said data processor and said output means, for generating a clock signal which oscillates substantially at said data rate and is synchronized to said second reference clock, said clock signal being used to clock said second data into said output means.
1 Assignment
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Accused Products
Abstract
A network (10) includes a broadband customer service module (B-CSM) (20). The B-CSM (20) includes a plurality of feeder interface cards (FICs) (36) and optical line cards (OLCS) (38) which are coupled together through a midplane assembly (34) so that each FIC (36) couples to all OLCs (38) and each OLC (38) couples to all FICs (36) through junctor groups (68). The B-CSM (20) interfaces many OC-12 SONET feeders to many OC-12 SONET lines. Within the B-CSM (20) circuit switching is performed electrically at an STS-1 rate. A reference clock which oscillates at a frequency lower than the data rate is routed with payload data so that it receives delays similar to those imposed on the payload data due to processing. At second stage switching fabrics (50) where data need to be extracted from signals flowing within the B-CSM (20), a clock regeneration circuit (32) generates a master clock signal oscillating at twice the data rate and phase synchronized to a delayed reference clock. A geometric compensation scheme corrects for timing skew which occurs when clocks and data are distributed to points or small areas from widely dispersed locations, and when clocks and data are distributed from points or small areas to widely dispersed locations.
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Citations
26 Claims
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1. A data transferring circuit for maintaining alignment between clock and data, said circuit comprising:
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input means for receiving first data at a data rate; a clock source configured to provide a reference clock which oscillates at a frequency less than said data rate, said clock source being configured so that said reference clock oscillates at a frequency of approximately one half said data rate; output means for presenting second data at substantially said data rate; a data processor for transforming said first data and said reference clock into said second data and a second reference clock, respectively; and a clock regenerator, coupled to said data processor and said output means, for generating a clock signal which oscillates substantially at said data rate and is synchronized to said second reference clock, said clock signal being used to clock said second data into said output means.
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2. A data transferring circuit for maintaining alignment between clock and data, said circuit comprising:
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input means for receiving first data at a data rate; a clock source configured to provide a reference clock which oscillates at a frequency less than said data rate; output means for presenting second data at substantially said data rate; a data processor for transforming said first data and said reference clock into said second data and a second reference clock, respectively, said data processor comprising a switch fabric having a first stage which is distributed among a plurality of first cards and a second stage which is distributed among a plurality of second cards, said first cards being oriented generally perpendicular to said second cards and each of said first cards coupling to all of said second cards; and a clock regenerator, coupled to said data processor and said output means, for generating a clock signal which oscillates substantially at said data rate and is synchronized to said second reference clock, said clock signal being used to clock said second data into said output means. - View Dependent Claims (3, 4)
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5. A data transferring circuit for maintaining alignment between clock and data, said circuit comprising:
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input means for receiving first data at a data rate; a clock source configured to provide a reference clock which oscillates at a frequency less than said data rate; output means for presenting second data at substantially said data rate; a data processor for transforming said first data and said reference clock into said second data and a second reference clock, respectively, said data processor comprising a switch fabric having a first stage which is distributed among a plurality of first modules and a second stage which is distributed among a plurality of second modules, said first modules coupling to said second modules at connection, and said first modules being substantially identical to one another and said second modules being substantially identical to one another; and a clock regenerator, coupled to said data processor and said output means, for generating a clock signal which oscillates substantially at said data rate and is synchronized to said second reference clock, said clock signal being used to clock said second data into said output means.
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6. A data transferring circuit for maintaining alignment between clock and data, said circuit comprising:
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input means for receiving first data at a data rate; a clock source configured to provide a reference clock which oscillates at a frequency less than said data rate; output means for presenting second data at substantially said data rate; a data processor for transforming said first data and said reference clock into said second data and a second reference clock, respectively, said data processor being distributed among a plurality of first and second modules, said first and second modules coupling together at connection points, said reference clock being routed to connection points on one of said second modules through signal paths of varying lengths, and third data, which are responsive to said first data and are presented to said connection points from said first modules, are routed on each of said second modules from said connection points through signal paths of varying lengths, wherein said varying lengths of said third data signal paths compensate for said varying lengths of said reference clock signal paths; and a clock regenerator, coupled to said data processor and said output means, for generating a clock signal which oscillates substantially at said data rate and is synchronized to said second reference clock, said clock signal being used to clock said second data into said output means. - View Dependent Claims (7, 8, 9, 10)
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11. A method of transferring data in synchronism with a master clock to maintain alignment between said master clock and said data, said method comprising the steps of:
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receiving first data at a data rate; generating a reference clock which is synchronized with said master clock and oscillates at a frequency less than said data rate; transforming said first data and said reference clock into second data and a second reference clock, respectively said first data being configured as a plurality of first data portions, said second data being configured as a plurality of second data portions, and said transforming step comprises the step of switching said first data portions into said second data portions; regenerating said master clock signal from said second reference clock; and using said regenerated master clock signal to clock said second data into a latch. - View Dependent Claims (12, 13)
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14. A method of transferring data in synchronism with a master clock to maintain alignment between said master clock and said data, said method comprising the steps of:
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receiving first data at a data rate; generating a reference clock which is synchronized with said master clock and oscillates at a frequency less than said data rate; transforming said first data and said reference clock into second data and a second reference clock, respectively said transforming step is performed throughout a plurality of first and second modules, said first and second modules coupling together at connection points; routing said reference clock to connection points on one of said second modules through signal paths of varying lengths; presenting third data to said connection points from said first modules, said third data being responsive to said first data; and routing said third data on each of said second modules from said connection points through signal paths of varying lengths, wherein said varying lengths of said third data signal paths compensate for said varying lengths of said reference clock signal paths; regenerating said master clock signal from said second reference clock; and using said regenerated master clock signal to clock said second data into a latch. - View Dependent Claims (15, 16, 17, 18)
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19. A data transferring circuit for maintaining alignment between clock and data, said circuit comprising:
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input means for receiving first data at a data rate; a clock source configured to provide a reference clock which oscillates at a frequency of approximately one half said data rate; output means for presenting second data at substantially said data rate; a switch fabric for switching said first data and said reference clock into said second data and a second reference clock, said switch fabric being configured to delay said first data to produce said second data and to delay said reference clock along with said first data to produce said second reference clock; and a clock regenerator, coupled to said switch fabric and said output means, for generating a clock signal which oscillates substantially at said data rate and is synchronized to said reference clock, said clock signal being used to clock said second data into said output means.
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20. A data transferring circuit for maintaining alignment between clock and data, said circuit comprising:
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input means for receiving first data at a data rate; a clock source configured to provide a reference clock which oscillates at a frequency less than said data rate; output means for presenting second data at substantially said data rate; a switch fabric for switching said first data and said reference clock into said second data and a second reference clock, said switch fabric being configured to delay said first data to produce said second data and to delay said reference clock along with said first data to produce said second reference clock, said switch fabric being distributed among a plurality of first and second cards, said first cards being oriented approximately perpendicular to said second cards and positioned so that each first card couples to all second cards at connection points, and said reference clock being routed to connection points on one of said second cards through signal paths of varying lengths; a clock regenerator, coupled to said switch fabric and said output means, for generating a clock signal which oscillates substantially at said data rate and is synchronized to said reference clock, said clock signal being used to clock said second data into said output means; and third data, which are responsive to said first data and are presented to said connection points from said first cards, are routed on each of said second cards from said connection points through signal paths of varying lengths, wherein said varying lengths of said third data signal paths compensate for said varying lengths of said reference clock signal paths. - View Dependent Claims (21, 22, 23, 24, 25, 26)
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Specification