Neural digital processor utilizing an approximation of a non-linear activation function

• US 5,796,925 A
• Filed: 02/06/1995
• Issued: 08/18/1998
• Est. Priority Date: 12/11/1991
• Status: Expired due to Fees

• Current Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Original Assignee: US Philips Corporation (Koninklijke Philips N.V.)
• Inventors: Deville, Yannick
• Primary Examiner(s): Davis, George B.
• Application Number:
  US08/384,191
• Time in Patent Office: 1,289 Days
• Field of Search: 395/27, 395/23, 395/24
• US Class Current: 706/43
• CPC Class Codes: G06N 3/048 Activation functions

Abstract

A neural digital processor (10) that includes circuitry (14) for applying a function ANLF to neural potentials. ANLF approximates a non-linear activation function NLF. The circuitry includes another neural processor which operates with another non-linear activation function CNLF. CNLF is a simple function, for example a ramp. The circuitry (14) may comprise elements (36₁, 36₂, 64) in common with apparatus (75) for calculating a derivative of the approximation function ANLF. The precision of approximation of the non-linear activation function NLF can be predetermined.

Claims

1. A neural digital processor (10), comprising:

a. an input (13) for receiving digital data and generating an output signal,

b. a neural unit (12) coupled to the input for calculating neural potentials, from the output signal, according to a function of the output signal and synaptic coefficients, said synaptic coefficients are weight connections either between neurons or between neurons and the input,

c. memory (16) for storing said synaptic coefficients,

d. means (14) for subjecting at least one of the neural potentials, designated POT, to at least one approximative non-linear activation function ANLF which is formed by n segments in order to produce at least one neural state, said means (14) comprising another neural digital processor which comprises;

I. means (20) for calculating n combinations, M_j =H_j ·

POT+Th_j, where

n is an integer;

j is an integer such that 1≦

j≦

n;

H_j are predetermined synaptic coefficients; and

Th_j are thresholds,

II. means (22) for calculating states S_j =F(M_j), using another non-linear function CNLF which is formed by

A. a segment F(x), where x is a running independent variable, which segment is not constant when x is situated in an interval (-x_min, x_max), and

B. two segments F(x)=F_max and F(x)=-F_min when x≧

x_max and x≦

-x_min, respectively,

III. means (24) for linearly combining the states with further synaptic coefficients D_j in order to produce said at least one neural state STAT.

2. A processor as claimed in claim 1, wherein the means (22) for calculating the states comprises:

means (36₁, 36₂,

     64) for detecting whether the combinations M_j are situated within the interval (-x_min,x_max) or outside this interval,

means (37) for calculating the states in this interval, and

means (37) for assigning, to the states, values F_max and -F_min, respectively, when M_j ≧

x_max and M_j≦

-x_min, respectively.

3. A processor as claimed in claim 2, wherein the means (37) comprises a table which stores predetermined values F(M_j) at addresses M_j.

4. A processor as claimed in claim 2, wherein

said other non-linear function CNLF is a ramp, and

the means (37) comprises transfer means (38,65) that apply the potential values M_j to the states S_j.

5. A processor as claimed in claim 1, wherein the other neural digital processor also comprises means (75) for calculating a derivative F'"'"' of the non-linear activation function ANLF.

6. A processor as claimed in claim 5, wherein the means (75) comprises at least one table which stores predetermined values of the states S'"'"'_j =F'"'"'(M_j) when the combinations M_j are situated within the interval (-x_min, x_max) and a value zero outside said interval.

7. A processor as claimed in claim 5, wherein

said other non-linear function CNLF is a ramp,

the means (75) comprises a block (70) that copies, for each state S'"'"'_j =F'"'"'(M_j), value of the corresponding synaptic coefficient H_j.

8. A processor as claimed in claim 5, wherein

said other non-linear function CNLF is a ramp,

the means (26) stores values H_j and D_j, for the calculation of the non-linear function ANLF, and values H_j and D_j ·

H_j for the derivative of the non-linear function ANLF, and

the means (75) comprises a block (70) whose inputs receive data of unit value.

9. A processor as claimed in claim 1, wherein the means (22) is used for successively calculating applications according to the non-linear function ANLF and according to ANLF'"'"'s derivative.

10. A processor as claimed in claim 1, wherein the neural unit (12) and the other neural processor (14) have common neurons.

11. A data processing system comprising a neural network comprising:

a. a unit for creating a neural potential from input data received by the unit, wherein the neural potential represents a sum of products, each respective one of the products resulting from a respective multiplication of a respective one of the input data by a respective synaptic coefficient;

b. non-linear function means for applying a non-linear function to the neural potential to create neuron output data, the non-linear function means comprising;

I. a plurality of further units, each respective one of the further units being for

A. supplying a respective further product resulting from multiplying the neural potential by a respective factor; and

B. applying a respective further non-linear function to the further product to create a respective outcome; and

II. combining means for linearly combining the respective outcomes to provide a value of the first non-linear function associated with said neural potential

said neural potential being an intermediate signal within a single neuron function whose external signal output is said neuron output data.

12. The system of claim 11, wherein each of said respective further non-linear functions comprises a respective ramp between two saturation values.

13. The system of claim 11 integrated in a single IC device.

14. A non-linear function device for use in creating at least one neuron output in a neural network processor, the device comprising:

a. means for receiving a neural potential signal which results from the sum of the products of a plurality of respective synaptic coefficients to a plurality of respective neuron input signals, which neural potential signal is an intermediate signal within a same neuron function as the at least one neuron output;

b. a plurality of means for sequentially applying a plurality of respective basic transfer functions to the neural potential signal for creating respective intermediate outcomes; and

c. combining means for linearly combining the respective outcomes to produce at least one non-linear output signal, said at least one non-linear output signal being an output of the at least one neuron.

15. A neural digital processor comprising:

a. input means for receiving digital data;

b. first means for storing a first plurality of synaptic coefficients;

c. a first neural unit for applying the first plurality of synaptic coefficients to an output signal of the input means, according to a stored neuron configuration to create at least one neural potential signal;

d. means for applying at least one respective first non-linear function to each of the at least one neural potential signal to create at least one respective neuron output, said means for applying at least one first non-linear function comprising another neural digital processor coupled to the first neural unit, said other neural digital processor comprising;

I. second means for storing a second plurality of synaptic coefficients;

II. a second neural unit for applying the second plurality of synaptic coefficients to the output signal of the first neural unit; and

III. means for applying at least one second non-linear function to an output signal of the second neural unit, said at least one second non-linear function being simpler than the non-linear function,

wherein each of the at least one neural potential signal is an intermediate signal within a respective single neuron function whose ultimate output is created by the means for applying at least one first respective non-linear function.

16. The processor of claim 15 further comprising feedback means coupling the means for applying at least one first non-linear function and the first neural unit, so that the at least one first non-linear function is iteratively appliable to realize neuron outputs of successive layers of the stored neuron configuration.

17. The processor of claim 15, wherein each of the at least one second non-linear function is a respective ramp.