ATM cell switch
First Claim
1. An ATM cell switch comprising a plurality of data input/output link controllers connected to external data links, each link controller comprising a leaky bucket processor to monitor and control cell flow rates, the leaky bucket processor comprising timer means for timing the arrival of each ATM cell, and calculating means to calculate the time interval between the reception of two consecutive cells on the same connection, means for storing a predetermined regular bucket increment, means for determining from the calculated time interval and from the predetermined regular bucket increment the resultant level in the bucket, and means for comparing the resultant level in the bucket with a predetermined maximum level and, if the maximum level will be exceeded, for discarding, or changing the Cell Loss Priority of, the current cell, wherein the leaky bucket processor includes means for performing the calculation of the resultant bucket level for a pair of buckets simultaneously.
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Accused Products
Abstract
An ATM cell switch includes a plurality of link controllers, each of which has a leaky bucket processor to monitor and control cell flow rates. Each of the leaky bucket processors includes a pair of buckets. Each processor times the arrival of each ATM cell in the respective link controller, calculates the time interval between the reception of two consecutive cells on the same connection, simultaneously determines the resultant level in both of the buckets from the calculated time interval and a stored predetermined regular bucket increment, compares the resultant level with a predetermined maximum level, and discards or changes the CLP of the current cell if the resultant level exceeds the predetermined maximum. According to a preferred embodiment of the invention, timing is effected with a 32-bit timer, but only the least significant 16-bits are used to time stamp cells. The time interval between two cells is calculated with two 16-bit adder/subtractors and two 16-bit buckets are thereby simultaneously controlled. The 32-bit routing table data is split into 16 lsb and 16 msb which are directed to respective of the adder/subtractors. A sequence of simultaneous operations in each of the adder/subtractors determine the eligibility of cells and the resultant bucket levels.
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Citations
6 Claims
- 1. An ATM cell switch comprising a plurality of data input/output link controllers connected to external data links, each link controller comprising a leaky bucket processor to monitor and control cell flow rates, the leaky bucket processor comprising timer means for timing the arrival of each ATM cell, and calculating means to calculate the time interval between the reception of two consecutive cells on the same connection, means for storing a predetermined regular bucket increment, means for determining from the calculated time interval and from the predetermined regular bucket increment the resultant level in the bucket, and means for comparing the resultant level in the bucket with a predetermined maximum level and, if the maximum level will be exceeded, for discarding, or changing the Cell Loss Priority of, the current cell, wherein the leaky bucket processor includes means for performing the calculation of the resultant bucket level for a pair of buckets simultaneously.
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6. A method of leaky bucket processing in an ATM cell switch, the method comprising:
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a) simultaneously recalculating the level values for a pair of different buckets in parallel; b) determining for each of the buckets whether the predetermined level has been exceeded; c) determining whether each bucket is valid for the current cell; d) determining whether the increment value should be added to the bucket value before writing back the new value to the bucket; and e) determining whether the cell is to be discarded and, if not, whether the Cell Priority is to be changed.
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Specification