ATM cell switch

• US 5,796,956 A
• Filed: 03/17/1995
• Issued: 08/18/1998
• Est. Priority Date: 03/18/1994
• Status: Expired due to Term

• Current Assignee: Ahead Communications Systems, Inc. (General DataComm Industries, Inc.)
• Original Assignee: General DataComm Advanced Research Centre Limited
• Inventors: Jones, Trevor
• Primary Examiner(s): Coleman, Eric
• Application Number:
  US08/406,300
• Time in Patent Office: 1,250 Days
• Field of Search: 395/200.01, 395/200.63, 395/200.65
• US Class Current: 709/233
• CPC Class Codes: H04L 12/5602 Bandwidth control in ATM Networks, e.g. leaky bucket
• CPC Class Codes: H04L 2012/5636 Monitoring or policing, e.g. compliance with allocated rate, corrective actions
• CPC Class Codes: H04L 2012/5637 Leaky Buckets
• CPC Class Codes: H04L 2012/5651 Priority, marking, classes
• CPC Class Codes: H04L 49/20 Support for services
• CPC Class Codes: H04L 49/30 Peripheral units, e.g. input or output ports
• CPC Class Codes: H04L 49/3009 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/3081 ATM peripheral units, e.g. policing, insertion or extraction
• CPC Class Codes: H04L 49/309 Header conversion, routing tables or routing tags
• CPC Class Codes: H04L 49/503 Policing

Abstract

An ATM cell switch includes a plurality of link controllers, each of which has a leaky bucket processor to monitor and control cell flow rates. Each of the leaky bucket processors includes a pair of buckets. Each processor times the arrival of each ATM cell in the respective link controller, calculates the time interval between the reception of two consecutive cells on the same connection, simultaneously determines the resultant level in both of the buckets from the calculated time interval and a stored predetermined regular bucket increment, compares the resultant level with a predetermined maximum level, and discards or changes the CLP of the current cell if the resultant level exceeds the predetermined maximum. According to a preferred embodiment of the invention, timing is effected with a 32-bit timer, but only the least significant 16-bits are used to time stamp cells. The time interval between two cells is calculated with two 16-bit adder/subtractors and two 16-bit buckets are thereby simultaneously controlled. The 32-bit routing table data is split into 16 lsb and 16 msb which are directed to respective of the adder/subtractors. A sequence of simultaneous operations in each of the adder/subtractors determine the eligibility of cells and the resultant bucket levels.

Claims

1. An ATM cell switch comprising a plurality of data input/output link controllers connected to external data links, each link controller comprising a leaky bucket processor to monitor and control cell flow rates, the leaky bucket processor comprising timer means for timing the arrival of each ATM cell, and calculating means to calculate the time interval between the reception of two consecutive cells on the same connection, means for storing a predetermined regular bucket increment, means for determining from the calculated time interval and from the predetermined regular bucket increment the resultant level in the bucket, and means for comparing the resultant level in the bucket with a predetermined maximum level and, if the maximum level will be exceeded, for discarding, or changing the Cell Loss Priority of, the current cell, wherein the leaky bucket processor includes means for performing the calculation of the resultant bucket level for a pair of buckets simultaneously.

2. An ATM cell switch according to claim 1, wherein the leaky bucket processor comprises means for carrying out the following steps upon receipt of a cell on a connection:

a) simultaneously recalculate the level values for a pair of different buckets in parallel;

b) determine for each of the buckets whether the predetermined level has been exceeded;

c) determine whether each bucket is valid for the current cell;

d) determine whether the increment value should be added to the bucket value before writing back the new value to the bucket; and

e) determine whether the cell is to be discarded and, if not, whether the Cell Priority is to be changed.

3. An ATM cell switch according to claim 1, wherein the timer means provides 32-bit time values, and the time difference is calculated using only the 16 least significant bits.

4. An ATM cell switch according to claim 1, wherein the leaky bucket processor comprises two 16-bit adder/subtractors to calculate the time interval between the reception of two cells on the same connection, and two magnitude comparators to compare the new levels of the buckets with the maximum permitted levels and to signal that the cell should be discarded if the maximum permitted level would be exceeded by inclusion of that cell.

5. An ATM cell switch according to claim 1, wherein a first bucket is arranged to monitor peak cell flow rates and a second bucket is arranged to monitor average cell flow rates.

6. A method of leaky bucket processing in an ATM cell switch, the method comprising:

a) simultaneously recalculating the level values for a pair of different buckets in parallel;

b) determining for each of the buckets whether the predetermined level has been exceeded;

c) determining whether each bucket is valid for the current cell;

d) determining whether the increment value should be added to the bucket value before writing back the new value to the bucket; and

e) determining whether the cell is to be discarded and, if not, whether the Cell Priority is to be changed.