Hierarchical fault modeling system and method

• US 5,796,990 A
• Filed: 09/15/1997
• Issued: 08/18/1998
• Est. Priority Date: 06/02/1995
• Status: Expired due to Term

• Current Assignee: Cadence Design Systems Incorporated (Cadence Group)
• Original Assignee: International Business Machines Corporation
• Inventors: Erle, Mark Alan, Graf, Matthew Christopher, Wohl, Peter
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): ROBERTS, ANDREW S
• Application Number:
  US08/929,578
• Time in Patent Office: 337 Days
• Field of Search: 395/500, 364/488, 364/489, 364/490, 364/491, 364/578, 371/26
• US Class Current: 716/103
• CPC Class Codes: G01R 31/318342 by preliminary fault modelling, e.g. analysis, simulation

Abstract

A system and method for generating a fault model for a logic circuit includes a data storage device for storing information relative to fault models or primitive elements in a logic circuit and for storing fault models for each level of design in a hierarchical logic circuit, a processor for processing the stored information relative to primitives and lower level fault models in the hierarchy for generating fault models for each succeeding higher level of design in the hierarchy, an input device for operator input of information to modify primitive fault models and a display subsystem for displaying various aspects of the hierarchical fault model generated in accordance with the present invention.

Claims

1. A method for hierarchically generating a fault model of a logic circuit according to a particular type of fault model, said method comprising the steps of:

generating fault models for primitive cells of the logic circuit according to the particular type of fault model, the primitive cells constituting a lowest level in the hierarchy of the logic circuit;

identifying a parent cell corresponding to a next cell in the hierarchy of the logic circuit;

creating a netlist of all connections in said parent cell;

seeding and identifying all possible faults in said parent cell, including equivalent faults and untestable faults, the untestable faults corresponding to faults which are not testable under the particular type of fault model;

collapsing the equivalent faults in said parent cell;

deleting untestable faults of all cells below said parent cell and their equivalent faults;

identifying new untestable faults by executing test software on said parent cell after untestable faults from cells below said parent cell have been removed from a fault model of said parent cell, and storing the new untestable faults in the fault model of said parent cell;

first testing to determine if said parent cell is a top cell in the hierarchy of said logic circuit;

second testing to determine if there is another cell not previously fault modeled at a same level in the hierarchy of said logic circuit as said parent cell;

identifying said another cell at said same level as said parent cell as a new parent cell;

repeating each step set forth above for said new parent cell; and

continuing said steps, beginning from the step of identifying the parent cell, until said top cell of said logic circuit has been fault modeled.

2. A system for hierarchically generating a fault model of a logic circuit according to a particular type of fault model, said system comprising:

a storage device for storing information relative to fault models for primitive cells in the logic circuit according to the particular type of fault model, the primitive cells constituting a lowest level in a hierarchical logic circuit, said storage device further for storing fault models for each level of design in the hierarchical logic circuit as the fault models are generated;

a processor, for generating the fault models for each succeeding higher level in the hierarchical logic circuit from the stored information until a top cell of the logic circuit has been fault modeled, said processor further including a means for creating a netlist of all connections of a parent cell in the hierarchy of the hierarchical logic circuit, wherein said storage device further includes means for storing identified untestable faults with a fault model of a parent cell;

one or more input devices for inputting information to modify one or more fault models for the primitive cells; and

a display subsystem for displaying various aspects of said hierarchical fault model.

3. The system according to claim 2, further comprising:

means for generating fault models for primitive cells of said logic circuit.

4. A system for hierarchically generating a fault model of a logic circuit according to a particular type of fault model, said system comprising:

means for generating fault models for primitive cells of the logic circuit according to the particular type of fault model, the primitive cells constituting a lowest level in the hierarchy of the logic circuit;

means for identifying a parent cell corresponding to a next cell in the hierarchy of the logic circuit;

means for creating a netlist of all connections in said parent cell;

means for seeding and identifying all possible faults in said parent cell, including equivalent faults and untestable faults, the untestable faults corresponding to faults which are not testable under the particular type of fault model;

means for collapsing the equivalent faults in said parent cell;

means for deleting untestable faults of all cells below said parent cell and their equivalent faults;

means for identifying new untestable faults by executing test software on said parent cell after untestable faults from cells below said parent cell have been removed from a fault model of said parent cell, and storing the new untestable faults in the fault model of said parent cell;

means for first testing to determine if said parent cell is a top cell in the hierarchy of said logic circuit;

means for second testing to determine if there is another cell not previously fault modeled at a same level in the hierarchy of said logic circuit as said parent cell;

means for identifying said another cell at said same level as said parent cell as a new parent cell;

means for repeating each step set forth above for said new parent cell; and

means for repeating each of the above steps until said top cell of said logic circuit has been fault modeled.