Method and apparatus for semiconductor device optimization using on-chip verification

• US 5,796,993 A
• Filed: 10/29/1996
• Issued: 08/18/1998
• Est. Priority Date: 10/29/1996
• Status: Expired due to Term

• Current Assignee: Freescale Semiconductor, Inc. (NXP Semiconductors NV)
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Maguire, Jeffrey E.
• Primary Examiner(s): Heckler, Thomas M.
• Application Number:
  US08/740,456
• Time in Patent Office: 658 Days
• Field of Search: 395/555, 395/558, 364/488-490, 364/550, 364/551.01, 364/569
• US Class Current: 713/500
• CPC Class Codes: G01R 31/3016 Delay or race condition test, e.g. race hazard test
• CPC Class Codes: G06F 1/04 Generating or distributing clock signals or signals derived directly therefrom

Abstract

An on-chip optimization circuitry (105) of a semiconductor device (100) provides a delay value to a delay generator (120) indicating an amount to delay an active signal edge. Based on the delay value, a modified device timing is created. Using the modified device timing, a portion of the semiconductor device (130) is tested using on-chip verification circuitry (110) to determine functionality. Based on functionality, a determination is made whether an optimal delay value has been found (550). If an optimal delay value has not been determined, a new delay value is used to produce a new modified device timing (516) and the sequence of testing and determining functionality is repeated until a optimized value has been determined.

Claims

1. A method for optimizing timing of an integrated circuit device, the method comprising the steps of:

(a) receiving a control delay value;

(b) producing a modified device timing, based on the control delay value;

(c) testing the modified device timing by using on-chip verification circuitry to determine if the integrated circuit device is a functional device;

(d) receiving a new control delay value, where the new control delay value replaces the control delay value and is different from the control delay value; and

(e) repeating steps (b)-(e) to determine an optimal control delay value for the integrated circuit device.

2. The method of claim 1 further comprising the step:

(f) saving the optimal control delay value.

3. The method of claim 2 further comprises the steps of:

(g) determining if a saved optimal delay value has been saved for the integrated circuit device, wherein if the saved optimal delay value does exist, using it as the control delay value, and where the saved optimal delay value does not exist performing the steps (b)-(e).

4. The method of claim 1 further wherein the modified device timing is produced by delaying an active edge of a device control signal based on the control delay value.

5. The method of claim 4 wherein step (b) further comprises delaying an active edge of a plurality of device control signals by the control delay value.

6. The method of claim 5 wherein the control delay value comprises a plurality of control delay values.

7. The method of claim 1 wherein the on-chip verification circuitry comprises Built-In Self Test (BIST) features.

8. A method for controlling timing of a device using verification circuitry within the device to verify device functionality, where the device has a control signal having an active edge, the active edge having an active edge location relative to a device clock, the method comprising:

(a) modifying the active edge location of the control signal;

(b) testing the device for functionality by using the verification circuitry within the device to determine if the device produces a valid result, where the valid result is indicative of the device operating in a predefined manner;

(c) repeating steps (a) through (c) until the active edge producing a valid result meets a predefined requirement; and

(d) storing the active edge location.

9. The method of claim 8 wherein the predefined requirement is the active edge nearest a device clock edge.

10. The method of claim 8 wherein the predefined requirement is the active edge furthest from a device clock edge.

11. A method for optimizing timing of a device, using circuitry within the device used to verify device functionality (verification circuitry), where the verification circuitry generates a valid signal if the device meets a predefined device criteria, the method comprising the steps of:

(a) setting a delay value of a variable delay controller to a maximum delay value, where the maximum delay value is a longest possible delay that can be represented by the variable delay controller;

(b) producing a modified device timing, using the variable delay controller by delaying an active edge of a device control signal by the delay value;

(c) testing the modified device timing by using the verification circuitry to determine if the device is functional, where the device is functional if the valid signal is generated;

(d) decreasing the delay value to produce a new delay value, where the new delay value replaces the delay value and is different from the delay value, and repeating steps (b)-(d) until the valid signal indicates that the device is not functioning; and

(f) increasing the delay value to establish an optimal delay value.

12. The method of claim 11 wherein the method further comprises the step of:

(g) storing the optimal delay value as a stored delay value.

13. The method of claim 12 wherein the method further comprises the step of:

(h) operating the device using the optimal delay value.

14. The method of claim 12 wherein the method further comprises the step of:

(h) determining if a stored delay value exist, and operating the device using the optimal delay value if the delay value does exist, and performing steps (b)-(d) if the delay value does not exist.

15. A method for optimizing timing of a device, using circuitry within the device used to verify device functionality (verification circuitry), where the verification circuitry generates a valid signal if the device meets a predefined device criteria, the method comprising the steps of:

(a) setting a delay value of a variable delay controller to a minimum delay value, where the minimum delay value is a shortest possible delay that can be represented by the variable delay controller;

(b) producing a modified device timing, using the variable delay controller by delaying an active edge of a device control signal by the delay value;

(c) testing the modified device timing by using the verification circuitry to determine if the device is functional, where the device is functional if the valid signal is generated;

(d) increasing the delay value to produce a new delay value, where the new delay value replaces the delay value and is different from the delay value, and repeating steps (b)-(d) until the valid signal indicates that the device is not functioning; and

(f) decreasing the delay value to establish an optimal delay value.

16. A method for optimizing timing of a device, using circuitry within the device used to verify device functionality (verification circuitry), where the verification circuitry generates a valid signal if the device meets a predefined device criteria, the method comprising the steps of:

(a) setting a delay value of a variable delay controller to a first delay value, where the first delay value is different than a predefined best delay value that can be represented by the variable delay controller;

(b) producing a modified device timing, using the variable delay controller by delaying an active edge of a device control signal by the delay value;

(c) testing the modified device timing by using the verification circuitry to determine if the device is functional, where the device is functional if the valid signal is generated; and

(d) modifying the delay value to produce a new delay value, where the new delay value replaces the delay value and is different from the delay value, and repeating steps (b)-(d) until the valid signal indicates that the device is not functioning.

17. A method for optimizing timing of a plurality of signals of a device using a Built-In Self Test (BIST) feature, where the BIST feature generates a valid signal if the device is functional, the method comprising the steps of:

(a) setting a plurality of variable delay controllers to a known delay value;

(b) setting a first variable delay controller of the plurality of variable delay controllers to a first delay value, where the first delay value is different than the known delay value;

(c) producing a modified device timing by using the first variable delay controller to modify at least one active edge of a device control signal by the first delay value;

(d) testing the modified device timing by using the BIST feature to determine if the device is functional, where the device is functional if the BIST feature generates the valid signal;

(e) setting the first variable delay controller to have a new delay value, where the new delay value replaces the first delay value and is different than the first delay value;

(f) repeating steps (b)-(e) until an optimal first delay value has been determined; and

(g) storing the optimal first delay value as a stored delay value; and

(h) repeating steps (a)-(h) for determining an optimal delay value for each of the plurality of variable delay controllers.

18. A method for optimizing timing of a plurality of signals of a device using a Built-In Self Test (BIST) feature, where the BIST feature generates a valid signal if the device is functional, the method comprising the steps of:

(a) setting a plurality of variable delay controllers to a known delay value;

(b) setting a first variable delay controller of the plurality of variable delay controllers to a first delay value, and a second variable delay controller of the plurality of variable delay controllers to a second delay value, where the first delay value is different than the known delay value;

(c) producing a modified device timing by using the first variable delay controller and the second variable delay controller to modify at least one active edge of device control signals based on the first delay value and the second delay value;

(d) testing the modified device timing by using the BIST feature to determine if the device is functional, where the device is functional if the BIST feature generates the valid signal;

(e) setting the first variable delay controller to have a new first delay value, and the second variable delay controller to have new second delay value, where the new first delay value replaces the first delay value and the new second delay value replaces the second delay value;

(f) repeating steps (b)-(e) until an optimal first delay value and second delay value has been determined; and

(g) storing the optimal first delay value and second delay value as a stored delay value; and

(h) repeating steps (a)-(h) for determining an optimal delay value for each of the plurality of variable delay controllers.

19. An apparatus for optimizing timing of a data processor device, where the apparatus comprises:

a Central Processing Unit (CPU) for executing computer instructions;

a Built-In Self Test (BIST) device, for performing BIST, coupled to the CPU and at least part of the device for determining functionality of the at least part of the data processing device, the BIST device producing a valid signal if the at least part of the device is functional;

a delay generator, having a variable delay controller, coupled the CPU and, receiving a device control signal, wherein the variable delay controller specifies a delay value to the delay generator, and wherein at least part of the device control signal is delayed by the delay generator based on the delay value of the variable delay controller to produce a modified device control signal 121; and

a memory unit coupled to the CPU, the BIST device, and the delay generator, for storing the computer instructions in a memory and for storing data in the memory, the computer instructions comprising;

computer instructions for setting the variable delay controller to a delay value;

computer instructions for performing BIST to determine if the modified device control signal produces the valid signal;

computer instructions for setting the variable delay controller to have a new delay value; and

computer instructions for repeating the computer instructions for performing BIST, setting the variable delay controller, and repeating, until an optimal delay value has been determined.

20. The device of claim 19 wherein the memory unit further comprising:

computer instructions for storing the optimal delay value as a stored delay value.

21. The device of claim 20 wherein the memory unit further comprising:

computer instructions for setting the variable delay controller to the stored delay value if the optimal delay value has been determined; and

computer instructions for not executing remaining computer instructions of claim 20 if the stored delay value exists.

22. The device of claim 19 wherein the BIST device further comprising:

computer instructions in the memory for determining functionality of the at least part of the device and for producing the valid signal if the at least part of the device is functional.

23. The device of claim 22 wherein the BIST device further comprising:

a BIST controller coupled to receive an initiate BIST signal, the BIST controller for determining functionality of the at least part of the device and for producing the valid signal if the at least part of the device is functional, wherein upon receipt of the initiate BIST signal, the BIST controller applies a test sequence to the at least part of the device, receives test results from the at least part of the device, and compares the test results to expected test results to determine if the at least part of the device is functional.

24. The apparatus of claim 19 further comprising:

circuitry for testing at least part of the data processor device, wherein the circuitry is coupled to a plurality of portions of the data processor device;

the delay generator is coupled to the plurality of portions of the device;

the memory unit is coupled to the plurality of parts of the device, the computer instructions further comprising;

computer instruction for using the circuitry for testing the plurality of parts of the device for functionality to determine if the valid signal is generated for the modified device control signal.

25. The apparatus of claim 19 wherein the memory resides internal to the device.

26. An apparatus for optimizing timing of a device, where the apparatus comprises:

a BIST controller coupled to receive an initiate BIST signal, the BIST controller for determining functionality of at least part of the device and for producing a valid signal if the at least part of the device is functional, wherein upon receipt of the initiate BIST signal, the BIST controller applies a test sequence to the at least part of the device, receives test results from the at least part of the device, and compares the test results to expected test results in order to determine if the at least part of the device is functional; and

a delay generator having a variable delay controller, the delay generator providing the initiate BIST signal, coupled to the BIST controller and to at least one device control signal, wherein the variable delay controller specifies a delay value to the delay generator, and wherein at least part of a device control signal is delayed by the delay generator based on the delay value of the variable delay controller to produce a modified device timing.

27. A method for speed sorting an integrated circuit device, the method comprising the steps of:

(a) receiving a semiconductor device to be tested;

(b) initializing a self-verification test, where in the self verification test is substantially performed by the integrated circuit device, and further comprises the steps of

(c) producing a modified device timing, based on a control delay value;

(d) testing the modified device timing by using on-chip verification circuitry to determine if the integrated circuit device is a functional device;

(e) generating a new control delay value, where the new control delay value replaces the control delay value and is different from the control delay value; and

(f) repeating steps (b)-(e) until an optimal control delay value for the device is determined;

(g) sorting the integrated circuit device based on the optimal control delay value.