Method and apparatus for fault tolerant BIOS addressing

• US 5,797,023 A
• Filed: 07/10/1997
• Issued: 08/18/1998
• Est. Priority Date: 10/17/1994
• Status: Expired due to Term

• Current Assignee: Hewlett-Packard Development Company, L.P. (HP Inc.)
• Original Assignee: Digital Equipment Corporation (HP Inc.)
• Inventors: Peterson, Kevin, Ciaffi, Marco, Hayes, Fidelma, Berman, Rachael, Shirron, Stephen F.
• Primary Examiner(s): Voeltz, Emanuel Todd
• Assistant Examiner(s): Richey, Michael T.
• Application Number:
  US08/891,249
• Time in Patent Office: 404 Days
• Field of Search: 395/750.06, 395/651, 395/652, 395/183.12, 395/183.18, 395/185.11, 395/653
• US Class Current: 713/324
• CPC Class Codes: G06F 11/1417 Boot up procedures
• CPC Class Codes: G06F 11/1666 where the redundant component is memory or memory area
• CPC Class Codes: G06F 11/22 Detection or location of defective computer hardware by testing during standby operation or during idle time, e.g. start-up testing

Abstract

An apparatus is described to provide a fault tolerant power-on of a computer system, using a BIOS memory containing a primary power-on system level configuration program for a computer system and a separate memory which contains a subset of the primary power-on system level configuration program. The subset program is accessed automatically, without human intervention, responding to a checksum detector of the BIOS memory data.

Claims

1. A method for providing a fault tolerant power-on of a computer system having a stored primary power-on system level configuration program, comprises the steps of:

accessing said primary power-on system level configuration program storage location;

performing a first check-sum calculation on said primary power-on system level configuration program;

executing said primary power-on system level configuration program to enable said computer system operations if said first check-sum operation indicates no failure in said primary power-on system level configuration program;

automatically accessing a secondary power-on system level configuration program storage location if said first checksum operation indicates a failure in said primary power-on system level configuration program data, and automatically notifying a system operator of said failure in said primary power-on system level configuration program;

performing a second check-sum calculation on said secondary power-on system level configuration program; and

executing said secondary power-on system level configuration program to enable said computer system operations if said second check-sum operation indicates no failure.

2. The method of claim 1, wherein said secondary power-on system level configuration program is a sub-set of said primary power-on system level configuration program and is stored in a separate memory location.

3. The method of claim 2, wherein said secondary power-on system level configuration program stored in said separate memory location, is the smallest sub-set of said primary power-on system level configuration program necessary to achieve minimal system operation.

4. The method of claim 1, wherein said secondary power-on system level configuration program is stored in a physically different memory structure than said primary configuration program.