Apparatus which prepares a master map portraying location of devices relative to bus interface circuits and copying the pertinent portion of the master map to each bus interface circuits

• US 5,797,036 A
• Filed: 04/29/1997
• Issued: 08/18/1998
• Est. Priority Date: 02/10/1994
• Status: Expired due to Fees

• Current Assignee: PDACO LIMITED
• Original Assignee: Elonex IP Holdings Limited
• Inventors: Kikinis, Dan
• Primary Examiner(s): Lee, Thomas C.
• Assistant Examiner(s): Huang, Po C.
• Application Number:
  US08/840,429
• Time in Patent Office: 476 Days
• Field of Search: 384/4, 380/25, 395/824, 395/856, 395/858, 395/829, 395/866
• US Class Current: 710/38
• CPC Class Codes: G06F 13/4004 Coupling between buses
• CPC Class Codes: G06F 13/4022 using switching circuits, e.g. switching matrix, connection or expansion network G06F13/4009 takes precedence
• CPC Class Codes: G06F 9/4411 Configuring for operating with peripheral devices; Loading of device drivers

Abstract

An I/O control system for a general-purpose computer having multiple bus branches separated by routing circuitry prepares a digital map of I/O device locations on the bus branches, and copies versions of the maps to registers in the routing circuitry on startup and reset. The routing maps provide immediate routing information for I/O requests issued by one or more CPUs in a system, allowing the routing circuitry between bus branches to immediately route requests to the proper device with a minimum of wait states. In one aspect I/O devices are polled for location at startup and reset, and in another aspect, a universal map protocol is a part of the BIOS or storage accessible by the BIOS, making a system self-configuring and providing the necessary information for the mapping for the routing circuitry.

Claims

1. In a computer system having three or more separate buses connected by bus interface circuits, a method for routing requests for devices connected to the separate buses, comprising steps of:

(a) preparing a digital master map which portrays the location relative to the bus interface circuits of each connected device;

(b) determining the portion of the master map pertinent to each bus interface circuit according to the buses connected by each interface circuit;

(c) copying the portion of the digital master map pertinent to each interface circuit to the associated bus interface circuit; and

(d) routing requests for connected devices at the bus interface circuits according to the map portions copied to the associated bus interface circuits.

2. The method of claim 1, wherein the step of preparing the digital map further comprises steps of:

polling connected devices to ascertain the location of installed devices on said separate buses, and

using the results of the polling step to prepare said digital map.

3. The method of claim 1, wherein the step of preparing the digital map further comprises steps of:

assigning each I/O port available in a system configuration a universal configuration port number;

storing a universal map protocol in a nonvolatile memory device; and

reading the universal map protocol by a system Basic Input Output System (BIOS) to prepare the digital map.

4. The method of claim 1 wherein the step of preparing the digital map further comprises steps of:

assigning a row of a memory array to each connected device;

enabling a bit in a first column of the memory array to indicate that the connected device assigned to the row of the enabled bit is installed and enabled; and

enabling bits in one or more additional columns of the memory array to indicate the location of each connected device relative to each bus interface circuit.

5. The method of claim 1 wherein a bus interface circuit has a first port and a second port, and the routing step further comprises steps of:

arranging the map portion copied to the bus interface circuit in a plurality of rows and a column, wherein each row corresponds to a connected device;

routing a request for a connected device from the first port to the second port if the map portion copied to the bus interface circuit has a first digital value in the column of the row corresponding to the requested connected device; and

blocking a request for a connected device from the first port to the second port if the map portion copied to the bus interface circuit has a second digital value, opposite the first digital value, in the column of the row corresponding to the requested connected device.

6. The method of claim 1 wherein a bus interface circuit has an input port and a plurality of output ports, and the routing step further comprises steps of:

arranging the map portion copied to the bus interface circuit in a plurality of rows and a plurality of columns, wherein each row corresponds to a connected device, and each column corresponds to one of the output ports;

routing a request for a connected device from the input port to an output port if the map portion copied to the bus interface circuit has a first digital value in the column corresponding to the output port in the row corresponding to the requested connected device; and

blocking a request for a connected device from the first port to an output port if the map portion copied to the bus interface circuit has a second digital value, opposite the first digital value, in each column of the row corresponding to the requested connected device.

7. The method of claim 1, wherein the step of preparing a digital map further comprises the steps of:

providing the computer system with a display having an interactive, on-screen interface;

entering the locations of installed connected devices on said buses using the on-screen interface; and

using the locations entered by the on-screen interface to prepare the digital map.

8. The method of claim 1, wherein the step of preparing the digital map is performed during startup and reset of the computer system.

9. The method of claim 1, further comprising, before the step of preparing a digital map, a step of establishing operation of the computer system.

10. The method of claim 1, wherein the step of preparing a digital map further comprises steps of:

assigning a row of a memory array to each device;

enabling a bit in a first column of the memory array to indicate that the device assigned to the row of the enabled bit is installed and enabled;

assigning one or more columns of the memory array to indicate sets of routing circuitry;

enabling bits in said one or more columns to indicate location of each connected device relative to each bus interface circuit; and

wherein the step of copying portions of the digital map further comprises steps of;

copying, for each particular bus interface circuit, the column of the memory array with enable bits for each connected device; and

copying the columns of the memory array indicating the location of each connected device relative to that particular bus interface circuit.

11. The method of claim 2 wherein the steps of preparing the digital map, copying and polling are performed by control routines that are a part of a Basic Input Output System of the computer system.

12. The method of claim 2 wherein the steps of preparing the digital map, copying and polling are performed by control routines which are not a part of the Basic Input Output System of the computer system, but which are accessed by the Basic Input Output System of the computer system.

13. The method of claim 2, wherein the step of polling connected devices is performed during startup and reset of the computer system.

14. The method of claim 3, wherein the step of reading the universal map protocol is performed during startup and reset of the computer system.

15. The method of claim 12, wherein the control routines are accessed by the Basic Input Output System during startup and reset of the computer system.

16. A Basic Input Output System (BIOS) for a computer system having three or more separate buses connected by bus interface circuits, comprising:

a non-volatile digital storage device coupled to the bus structure;

initialization code for initializing elements of the computer system during startup and reset of the computer system;

input/output code for controlling communication with devices connected to the computer system; and

mapping code adapted for preparing a digital master map which portrays the location of each connected device installed on any one of the multiple buses relative to each bus interface circuit, for determining a portion of the master map pertinent to each bus interface circuit according to the buses connected by each interface circuit, and for copying the pertinent portions of the digital master map to the associated bus interface circuits, so that routing requests for connected devices at the bus interface circuits are routed according to the map portions copied to the particular bus interface circuits.

17. A Basic Input Output System as in claim 16 wherein the mapping code sequences are adapted for polling all bus ports on the buses for ascertaining the location of connected devices, and for using the results of the polling operation to prepare the digital map.

18. A Basic Input Output System as in claim 16, further comprising

a plurality of I/O ports wherein each I/O port is assigned a universal configuration port number;

a memory device which stores a universal map protocol which is used for preparing the digital map.

19. A Basic Input Output System as in claim 16 wherein the digital map portions comprise a row assigned to each connected device, an enable bit column indicating connected devices installed and enabled, and one or more routing bit columns indicating the location of each connected device relative to each bus interface circuit.

20. A Basic Input Output System as in claim 16 wherein a bus interface circuit has a first port coupled to a first bus and a second port coupled to a second bus, and the digital map portion copied to the bus interface circuit has one row for each connected device and one routing bit column, wherein a first digital value is stored in the routing bit column in each row assigned to a connected device which is coupled to the second bus and wherein a second digital value, opposite the first digital value, is stored in the routing bit column in each row assigned to a connected device which is coupled to the first bus.

21. A Basic Input Output System as in claim 16 wherein a bus interface circuit has more than two ports connecting more than two buses, and the digital map copied to the bus interface circuit has plural routing bit columns for each connected device of the system.

22. A Basic Input Output System as in claim 18 wherein the memory device is a programmable read-only memory separate from the Basic Input Output System, wherein the programmable read-only memory is accessed by the Basic Input Output System to prepare the digital map.

23. A computer system comprising:

a central processing unit (CPU);

a bus system coupled to said CPU wherein said bus system comprises three or more buses coupled by bus interface circuits;

a plurality of devices coupled to buses of said bus system; and

a Basic Input Output System coupled to said CPU for providing basic operating instructions for said CPU;

wherein said Basic Input Output System is configured for preparing a digital master map during operation of the computer system, wherein the digital master map portrays the location of each connected device relative to each bus interface circuit, for determining a portion of the digital master map pertinent to each bus interface circuit, and for copying the pertinent portions of said digital master map to the associated bus interface circuits, so that routing requests for connected devices at the bus interface circuits are routed according to the map portions copied to the particular bus interface circuits.

24. A computer system as in claim 23 wherein said Basic Input Output System is configured for polling all bus ports on the buses for ascertaining the location of connected devices, and for using the results of the polling operation to prepare said digital map.

25. A computer system as in claim 23;

further comprising;

a plurality of I/O ports, wherein each I/O port is assigned a universal configuration port number;

a memory device which stores a universal map protocol which is used for preparing the digital map.

26. A computer system as in claim 23 wherein the digital map portions comprise a row assigned to each connected device, an enable bit column indicating connected devices installed and enabled, and one or more routing bit columns indicating the location of each connected device relative to each set of routing circuitry.

27. A computer system as in claim 25 wherein the memory device is a programmable read-only memory separate from the Basic Input Output System, wherein the programmable read-only memory is accessed by the Basic Input Output System to prepare the digital map.

28. A computer system as in claim 26 wherein a bus interface circuit has a first port coupled to a first bus and a second port coupled to a second bus, and the digital map portion copied to the bus interface circuit has one row for each connected device and one routing bit column, wherein a first digital value is stored in the routing bit column in each row assigned to a connected device which is coupled to the second bus and wherein a second digital value, opposite the first digital value, is stored in the routing bit column in each row assigned to a connected device which is coupled to the first bus.

29. A computer system as in claim 26 wherein a bus interface circuit has more than two ports connecting more than two buses, and the digital map copied to the bus interface circuit has plural routing bit columns for indicating the locations of connected devices relative to the bus interface circuit.

30. A computer system comprising:

a central processing unit (CPU);

a bus system coupled to said CPU comprising three or more buses coupled by bus interface circuits;

a plurality of devices coupled to said buses;

a monitoring unit adapted for monitoring said plurality of buses for identifying the location of each of said plurality of devices relative to each bus interface circuit;

memory coupled to said monitoring unit for storing a digital master map, said digital master map portraying the location of each of said plurality of devices relative to each bus interface circuit; and

registers coupled to each of said bus interface circuits, wherein a portion of said digital master map particular to each of said bus interface circuits according to the buses joined by each said interface circuit is copied to the registers coupled to said particular bus interface circuit;

wherein requests for devices by said CPU are routed to said devices according to the portions of said digital master map copied to the registers coupled to each of said bus interface circuits.

31. A computer system comprising:

three buses;

two bus interface circuits connecting the three buses; and

a mapper;

wherein the mapper prepares a master map of devices connected to the three buses, the map portraying the location of the devices on the three buses relative to the bus interface circuit, determines a portion of the master map pertinent to each interface circuit according to the buses connected by the interface circuit, and copies the pertinent portion of the map to the associated bus interface circuit.