System for managing the transfer of data between FIFOs within pool memory and peripherals being programmable with identifications of the FIFOs

• US 5,797,043 A
• Filed: 03/13/1996
• Issued: 08/18/1998
• Est. Priority Date: 03/13/1996
• Status: Expired due to Term

• Current Assignee: Altera Corporation (Intel Corporation)
• Original Assignee: Diamond Multimedia Systems Incorporated (SONICblue Incorporated)
• Inventors: Lewis, Adrian, Begur, Sridhar, Kilbourn, Thomas E., Spencer, Donald J., Gochnauer, Daniel B., Gifford, James K.
• Primary Examiner(s): Meky, Moustafa M.
• Application Number:
  US08/615,682
• Time in Patent Office: 888 Days
• Field of Search: 395/250, 395/800, 395/821, 395/822, 395/823, 395/835, 395/872, 395/826, 395/833, 395/873, 395/874, 395/875, 395/876, 395/877
• US Class Current: 710/56
• CPC Class Codes: G06F 13/18 based on priority control G06F13/1605 takes precedence

Abstract

A data transfer control system including a pool memory, a plurality of peripheral devices, and a transfer controller. The pool memory provides for the storage of data in a plurality of FIFOs formed within the pool memory. The plurality of peripheral devices are coupleable to the pool memory to provide for the transfer of data between programmatically associated FIFOs and peripheral devices. The transfer controller is coupled to the pool memory and to the peripheral devices for selectively managing the transfer of data between the FIFOs and the peripheral devices. The transfer controller includes a distributed signaling system coupled to the peripheral devices to permit the broadcast of status information reflective of a transfer of data relative to a predetermined FIFO to the peripheral devices.

Claims

1. A data transfer control system comprising:

a) a pool memory providing for the storage of data in a plurality of FIFOs formed within said pool memory;

b) a plurality of peripherals coupleable to said pool memory for the transfer of data between programmatically associated ones of said FIFOs and said peripherals said peripherals being programmable with identifications of said FIFOs; and

c) a transfer controller coupled to said pool memory and to said peripherals for selectively managing the transfer of data between said FIFOs and said peripherals, said transfer controller including a distributed signaling system coupled to said peripherals to permit the broadcast of status information reflective of a transfer of data relative to a predetermined FIFO to said peripherals, said status information including a predetermined identifier of said predetermined FIFO.

2. The data transfer control system of claim 1 wherein said peripherals determiners from said status information whether to request an access of said pool memory to transfer data with respect to said predetermined FIFO.

3. The data transfer control system of claim 2 wherein said transfer controller includes a memory pool arbiter and wherein said peripherals selectively present requests to access said memory pool in response to said status information.

4. The data transfer control system of claim 3 wherein said FIFOs are allocable within said memory pool and wherein said transfer controller includes a FIFO control store that maintains sets of read and write pointers into said memory pool for each of said FIFOs.

5. The data transfer control system of claim 4 wherein said peripherals each include a control register that provides programmable storage for a FIFO identifier and a transfer direction flag with respect to each of said FIFOs associated with each of said peripherals.

6. The data transfer control system of claim 5 wherein each of said FIFO identifiers and each corresponding set of said read and write pointers permit said transfer controller to manage data transfers between said peripherals and said FIFOs.

7. The data transfer control system of claim 6 wherein each of said peripherals includes an internal FIFO for staging data in the process of transfer between said peripherals and said memory pool.

8. A data transfer controller comprising:

a) a central memory including a plurality of memory blocks wherein said memory blocks are referencable by memory block identifiers;

b) a plurality of data transfer devices coupleable through a memory bus to said central memory to permit data transfer accesses between a predetermined memory block and a predetermined data transfer device, said data transfer devices including control registers providing for the programmable storage of memory block identifiers and data buffers providing for the transient storage of data; and

c) control logic coupled to said memory bus for selectively providing said predetermined data transfer device with access to said predetermined memory block, said control logic providing update data reflective of an access of said predetermined memory block to each of said data transfer devices.

9. The data transfer controller of claim 8 wherein said update data includes a predetermined memory block identifier corresponding to said predetermined memory block.

10. The data transfer controller of claim 9 further comprising a central memory arbiter coupled to said data transfer devices, wherein said data transfer devices are responsive to a match between said predetermined memory block identifier and the memory block identifiers stored in said control registers, said predetermined data transfer device responding to a match with said predetermined memory block identifier by issuing an access request to said central memory arbiter.