Method and apparatus for complex bandpass filtering and decimation in ultrasound beamformer

• US 5,797,847 A
• Filed: 12/30/1996
• Issued: 08/25/1998
• Est. Priority Date: 12/30/1996
• Status: Expired due to Term

• Current Assignee: General Electric Company
• Original Assignee: General Electric Company
• Inventors: Miller, Steven C., Milon, Daniel, Lillegard, Gregory A.
• Primary Examiner(s): Jaworski, Francis
• Assistant Examiner(s): IMAM, ALI M
• Application Number:
  US08/774,666
• Time in Patent Office: 603 Days
• Field of Search: 600/443, 600/453, 600/447, 600/555, 600/441, 600/455, 600/454, 375/261, 367/138, 367/105, 367/135, 342/195, 327/254
• US Class Current: 600/447
• CPC Class Codes: G01N 2291/044 Internal reflections (echoes), e.g. on walls or defects
• CPC Class Codes: G10K 11/346 using phase variation
• CPC Class Codes: H03H 17/0664 where the output-delivery frequency is lower than the input sampling frequency, i.e. decimation

Abstract

A phased array sector scanning ultrasonic system includes a separate beamformer channel for each respective element in an ultrasonic transducer array. Each beamformer channel has a three-stage complex FIR filter downstream of an analog-to-digital converter. Each filter circuit stage has a register pipeline, an in-phase FIR filter and a quadrature FIR filter. The first stage only has real samples, so there is a single pipeline. The other stages have complex inputs composed of in-phase (real) and quadrature (imaginary) samples, requiring a pipeline for each. Each register pipeline is made up of a multiplicity of registers connected in series. The number of registers in a given pipeline must equal the number of taps being used on the FIR filter immediately downstream of the register pipeline. The registers are clocked in synchronism and store successive echo data samples. Each register in the pipeline has an output connected to a respective tap of the corresponding FIR filter. In the second and third stages, the taps on the FIR filters receive data samples consisting of a real data sample from the I pipeline and/or an imaginary data sample from the Q pipeline. These complex data samples are multiplied by complex filter coefficients and the products are summed to form a respective filtered data sample output for each stage.

Claims

1. A complex FIR filter circuit comprising:

a first register pipeline clocked at a first sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from an input stream of digital samples;

a first filtering means for outputting in at least every other sampling period an in-phase filtered digital sample and a quadrature filtered digital sample derived from said plurality of successive digital samples output by said first register pipeline by applying a first set of complex filter coefficients;

a second register pipeline clocked at a second sampling rate less than said first sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from said in-phase filtered digital samples output by said first filtering means;

a third register pipeline clocked at said second sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from said quadrature filtered digital samples output by said first filtering means; and

a second filtering means for outputting in at least every other sampling period an in-phase filtered digital sample and a quadrature filtered digital sample derived from said plurality of successive digital samples output by said second register pipeline and said plurality of successive digital samples output by said third register pipeline by applying a second set of complex filter coefficients.

2. The complex FIR filter circuit as defined in claim 1, wherein said first filtering means comprise:

first shifting/inverting means for bit shifting and/or inverting said respective plurality of successive digital samples output by said first register pipeline in accordance with a first set of bit shift and/or invert values derived from said first set of complex filter coefficients; and

first adding means for adding said shifted/inverted digital samples output by said first shifting means.

3. The complex FIR filter circuit as defined in claim 1, further comprising:

a fourth register pipeline clocked at a third sampling rate less than said second sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from said in-phase filtered digital samples output by said second filtering means;

a fifth register pipeline clocked at said third sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from said quadrature filtered digital samples output by said second filtering means; and

a third filtering means for outputting in at least every other sampling period a respective in-phase filtered digital sample and a respective quadrature filtered digital sample derived from said respective plurality of successive digital samples output by said fourth register pipeline and said respective plurality of successive digital samples output by said fifth register pipeline by applying a third set of complex filter coefficients.

4. The complex FIR filter circuit as defined in claim 1, wherein said first filtering means comprise:

a first in-phase FIR filter for outputting in at least every other sampling period a respective in-phase filtered digital sample derived from said respective plurality of successive digital samples output by said first register pipeline by bit shifting and/or inverting in accordance with a first set of bit shift and/or invert values derived from said first set of complex filter coefficients; and

a first quadrature FIR filter for outputting in at least every other sampling period a respective quadrature filtered digital sample derived from said respective plurality of successive digital samples output by said first register pipeline by bit shifting and/or inverting in accordance with a second set of bit shift and/or invert values derived from said first set of complex filter coefficients.

5. The complex FIR filter circuit as defined in claim 2, wherein said first filtering means further comprises:

second shifting/inverting means for bit shifting and/or inverting said respective plurality of successive digital samples output by said first register pipeline in accordance with a second set of bit shift and/or invert values derived from said first set of complex filter coefficients;

second adding means for adding said shifted/inverted digital samples output by said second shifting means; and

a multiplexer having first and second inputs coupled to receive outputs from said first and second adding means respectively.

6. The complex FIR filter circuit as defined in claim 2, wherein said second filtering means comprise:

second shifting/inverting means for bit shifting and/or inverting said respective plurality of successive digital samples output by said second and third register pipelines in accordance with second and third sets of bit shift and/or invert values derived from said second set of complex filter coefficients; and

second adding means for adding said shifted/inverted digital samples output by said second shifting means.

7. The complex FIR filter circuit as defined in claim 2, wherein said first adding means comprises a Wallace tree adder.

8. The complex FIR filter circuit as defined in claim 4, wherein said second filtering means comprise:

a second in-phase FIR filter for outputting in at least every other sampling period a respective in-phase filtered digital sample derived from said respective plurality of successive digital samples output by said second register pipeline and said respective plurality of successive digital samples output by said third register pipeline by bit shifting and/or inverting in accordance with a third set of bit shift and/or invert values derived from said second set of complex filter coefficients; and

a second quadrature FIR filter for outputting in at least every other sampling period a respective quadrature filtered digital sample derived from said respective plurality of successive digital samples output by said second register pipeline and said respective plurality of successive digital samples output by said third register pipeline by bit shifting and/or inverting in accordance with a fourth set of bit shift and/or invert values derived from said second set of complex filter coefficients.

9. A beamformer comprising a multiplicity of beamformer channels, a summer having a multiplicity of inputs respectively coupled to said multiplicity of beamformer channels, and a complex FIR filter circuit having an input connected to an output of said summer, wherein said complex FIR filter circuit comprises:

a first register pipeline clocked at a first sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from an input stream of digital samples;

a first filtering means for outputting in at least every other sampling period an in-phase filtered digital sample and a quadrature filtered digital sample derived from said plurality of successive digital samples output by said first register pipeline by applying a first set of complex filter coefficients;

a second register pipeline clocked at a second sampling rate less than said first sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from said in-phase filtered digital samples output by said first filtering means;

a third register pipeline clocked at said second sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from said quadrature filtered digital samples output by said first filtering means; and

a second filtering means for outputting in at least every other sampling period an in-phase filtered digital sample and a quadrature filtered digital sample derived from said plurality of successive digital samples output by said second register pipeline and said plurality of successive digital samples output by said third register pipeline by applying a second set of complex filter coefficients.

10. The beamformer as defined in claim 9, wherein said first filtering means comprise:

first shifting/inverting means for bit shifting and/or inverting said respective plurality of successive digital samples output by said first register pipeline in accordance with a first set of bit shift and/or invert values derived from said first set of complex filter coefficients; and

first adding means for adding said shifted/inverted digital samples output by said first shifting means.

11. The beamformer as defined in claim 9, further comprising:

a fourth register pipeline clocked at a third sampling rate less than said second sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from said in-phase filtered digital samples output by said second filtering means;

a fifth register pipeline clocked at said third sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from said quadrature filtered digital samples output by said second filtering means; and

a third filtering means for outputting in at least every other sampling period a respective in-phase filtered digital sample and a respective quadrature filtered digital sample derived from said respective plurality of successive digital samples output by said fourth register pipeline and said respective plurality of successive digital samples output by said fifth register pipeline by applying a third set of complex filter coefficients.

12. The beamformer as defined in claim 9, wherein said first filtering means comprise:

a first in-phase FIR filter for outputting in at least every other sampling period a respective in-phase filtered digital sample derived from said respective plurality of successive digital samples output by said first register pipeline by bit shifting and/or inverting in accordance with a first set of bit shift and/or invert values derived from said first set of complex filter coefficients; and

a first quadrature FIR filter for outputting in at least every other sampling period a respective quadrature filtered digital sample derived from said respective plurality of successive digital samples output by said first register pipeline by bit shifting and/or inverting in accordance with a second set of bit shift and/or invert values derived from said first set of complex filter coefficients.

13. The beamformer as defined in claim 10, wherein said first filtering means further comprises:

second shifting/inverting means for bit shifting and/or inverting said respective plurality of successive digital samples output by said first register pipeline in accordance with a second set of bit shift and/or invert values derived from said first set of complex filter coefficients;

second adding means for adding said shifted/inverted digital samples output by said second shifting means; and

a multiplexer having first and second inputs coupled to receive outputs from said first and second adding means respectively.

14. The beamformer as defined in claim 10, wherein said second filtering means comprise:

second shifting/inverting means for bit shifting and/or inverting said respective plurality of successive digital samples output by said second and third register pipelines in accordance with second and third sets of bit shift and/or invert values derived from said second set of complex filter coefficients; and

second adding means for adding said shifted/inverted digital samples output by said second shifting means.

15. The beamformer as defined in claim 10, wherein said first adding means comprises a Wallace tree adder.

16. The beamformer as defined in claim 12, wherein said second filtering means comprise:

a second in-phase FIR filter for outputting in at least every other sampling period a respective in-phase filtered digital sample derived from said respective plurality of successive digital samples output by said second register pipeline and said respective plurality of successive digital samples output by said third register pipeline by bit shifting and/or inverting in accordance with a third set of bit shift and/or invert values derived from said second set of complex filter coefficients; and

a second quadrature FIR filter for outputting in at least every other sampling period a respective quadrature filtered digital sample derived from said respective plurality of successive digital samples output by said second register pipeline and said respective plurality of successive digital samples output by said third register pipeline by bit shifting and/or inverting in accordance with a fourth set of bit shift and/or invert values derived from said second set of complex filter coefficients.

17. An ultrasonic imaging system comprising a transducer array, a beamformer coupled to said transducer array, a signal processor coupled to said beamformer, a scan converter coupled to said signal processor, and a display monitor coupled to said scan converter, wherein said transducer array comprises a multiplicity of transducer elements and said beamformer comprises a multiplicity of beamformer channels, switching circuitry for selectively coupling said beamformer channels to said transducer elements, summing means having a multiplicity of inputs respectively coupled to said multiplicity of beamformer channels, and a complex FIR filter circuit having an input connected to an output of said summer, wherein said complex FIR filter circuit comprises:

a first register pipeline clocked at a first sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from an input stream of digital samples;

a first filtering means for outputting in at least every other sampling period an in-phase filtered digital sample and a quadrature filtered digital sample derived from said plurality of successive digital samples output by said first register pipeline by applying a first set of complex filter coefficients;

a second register pipeline clocked at a second sampling rate less than said first sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from said in-phase filtered digital samples output by said first filtering means;

a third register pipeline clocked at said second sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from said quadrature filtered digital samples output by said first filtering means; and

a second filtering means for outputting in at least every other sampling period an in-phase filtered digital sample and a quadrature filtered digital sample derived from said plurality of successive digital samples output by said second register pipeline and said plurality of successive digital samples output by said third register pipeline by applying a second set of complex filter coefficients.

18. The ultrasonic imaging system as defined in claim 17, wherein said first filtering means comprise:

first shifting means for bit shifting and/or inverting said respective plurality of successive digital samples output by said first register pipeline in accordance with a set of bit shift and/or invert values derived from said first set of complex filter coefficients; and

first adding means for adding said shifted/inverted digital samples output by said second shifting means.

19. The ultrasonic imaging system as defined in claim 17, wherein said complex FIR filter circuit further comprises:

a fourth register pipeline clocked at a third sampling rate less than said second sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from said in-phase filtered digital samples output by said second filtering means;

a fifth register pipeline clocked at said third sampling rate and having a plurality of outputs for outputting in each sampling period a respective plurality of successive digital samples derived from said quadrature filtered digital samples output by said second filtering means; and

a third filtering means for outputting in at least every other sampling period a respective in-phase filtered digital sample and a respective quadrature filtered digital sample derived from said respective plurality of successive digital samples output by said fourth register pipeline and said respective plurality of successive digital samples output by said fifth register pipeline by applying a third set of complex filter coefficients.

20. A method of downsampling digital samples in an ultrasound beamformer, comprising the steps of:

acquiring a stream of digital data samples;

clocking said digital data samples in succession through a first register pipeline at a first sampling rate, said first register pipeline storing a respective multiplicity of digital data samples during each successive sampling period, each multiplicity of digital data samples being output in parallel in response to a respective clock signal output at said first sampling rate;

bit shifting and/or inverting each multiplicity of digital data samples in accordance with a first set of bit shift and/or invert values derived from a first set of complex filter coefficients to produce a first multiplicity of filtered digital data samples;

bit shifting and/or inverting each multiplicity of digital data samples in accordance with a second set of bit shift and/or invert values derived from said first set of complex filter coefficients to produce a second multiplicity of filtered digital data samples;

adding said respective first multiplicity of bit shifted/inverted digital data samples to produce a respective first-stage in-phase digital data sample;

adding said respective second multiplicity of bit shifted/inverted digital data samples to produce a respective first-stage quadrature digital data sample;

clocking said respective first-stage in-phase digital data samples in succession through a second register pipeline at a second sampling rate less than said first sampling rate, said second register pipeline storing a respective multiplicity of in-phase digital data samples during each successive sampling period, each multiplicity of in-phase digital data samples being output in parallel in response to a respective clock signal output at said second sampling rate;

clocking said respective first-stage quadrature digital data samples in succession through a third register pipeline at said second sampling rate, said second register pipeline storing a respective multiplicity of quadrature digital data samples during each successive sampling period, each multiplicity of quadrature digital data samples being output in parallel in response to said respective clock signal output at said second sampling rate;

bit shifting and/or inverting each multiplicity of in-phase digital data samples from said second register pipeline and each multiplicity of quadrature digital data samples from said third register pipeline in accordance with a third set of bit shift and/or invert values derived from a second set of complex filter coefficients to produce a third multiplicity of filtered digital data samples;

bit shifting and/or inverting each multiplicity of in-phase digital data samples from said second register pipeline and each multiplicity of quadrature digital data samples from said third register pipeline in accordance with a fourth set of bit shift and/or invert values derived from said second set of complex filter coefficients to produce a fourth multiplicity of filtered digital data samples;

adding said respective third multiplicity of bit shifted/inverted digital data samples to produce a respective second-stage in-phase digital data sample; and

adding said respective fourth multiplicity of bit shifted/inverted digital data samples to produce a respective second-stage quadrature digital data sample.