Method for forming conductors in integrated circuits

• US 5,798,300 A
• Filed: 05/15/1997
• Issued: 08/25/1998
• Est. Priority Date: 07/07/1995
• Status: Expired due to Term

• Current Assignee: Bell Semiconductor, LLC (Hilco Inc. (d/b/a Hilco Global))
• Original Assignee: Lucent Technologies, Inc. (Nokia Corporation)
• Inventors: Chittipeddi, Sailesh, Merchant, Sailesh Mansinh
• Primary Examiner(s): Niebling, John
• Assistant Examiner(s): BILODEAU, THOMA
• Application Number:
  US08/857,079
• Time in Patent Office: 467 Days
• Field of Search: 438/636, 438/627, 438/628, 438/642, 438/645, 438/644, 438/648, 438/688, 438/647, 204/192.17, 204/192.23
• US Class Current: 438/627
• CPC Class Codes: H01L 21/76877 Filling of holes, grooves or trenches, e.g. vias, with conductive material

Abstract

A method of forming electromigration resistant integrated circuit runners is disclosed. A collimated beam of particles is directed toward a substrate to form a metal nucleating layer. Then a non-collimated beam is used to form the rest of the metal layer. Then the layers are patterned to form runners.

Claims

1. A method of integrated circuit fabrication comprising:

forming a layer overlying a substrate by;

directing a collimated beam of aluminum particles at said substrate, thereby forming a first conductive layer;

then sputtering non-collimated aluminum particles at said substrate, thereby forming a second conductive layer contacting said first conductive layer; and

depositing a third conductive layer of polysilicon over said second conductive layer such that said third conductive layer contacts said second conductive layer.

2. The method of claim 1 further including the step of forming a conductive runner by patterning said first and second layers together.

3. The method of claim 1 in which said first conductive layer has a thickness of 50-5000Å

.

4. The method of claim 1 in which said second conductive layer has a thickness of 2 kÅ

-10 kÅ

.

5. The method of claim 1 in which said substrate is conductive and said substrate is partially covered by a dielectric, said dielectric having vias which expose portions of said substrate and in which said first and second conductive layers substantially fill said via and cover said dielectric.

6. The method of claim 1 further including the steps of forming one or more conductive layers between said substrate and said first conductive layer.

7. The method of claim 6 in which said conductive layer is chosen from the group consisting of titanium nitride, a refractory metal silicide and titanium.

8. The method of claim 6 further including the step of forming a bilayer before forming said first conductive layer.

9. The method of claim 8 in which said bilayer is titanium nitride overlying titanium.

10. The method of claim 1 further including the step of forming at least one conductive layer over said second conductive layer.