Standard semiconductor cell with contoured cell boundary to increase device density

• US 5,798,541 A
• Filed: 03/17/1997
• Issued: 08/25/1998
• Est. Priority Date: 12/02/1994
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Jassowski, Michael
• Primary Examiner(s): Thomas, Tom
• Assistant Examiner(s): Hardy, David B.
• Application Number:
  US08/818,414
• Time in Patent Office: 526 Days
• Field of Search: 257/202, 257/204, 257/206, 257/207, 257/211
• US Class Current: 257/202
• CPC Class Codes: H01L 27/0207 Geometrical layout of the components, e.g. computer aided design; custom LSI, semi-custom LSI, standard cell technique

Abstract

A layout arrangement which provides a contouring of cells that allows the individual rectangular cell boundaries to overlap each other to a point at which individual device edges abut one another thereby utilizing die area which is normally lost to use. In order to attain this result, a new cell contour boundary is described about each cell at the edge of each individual device adjacent the exterior of the cell at a distance at which other cells may abut without disturbing the operation of the cell. Then, computer implemented processes are applied to cause the cells to fit abutting the newly described boundaries.

Claims

1. A non-rectangular contour semiconductor cell wherein the contour allows for density optimization, the contoured cell comprising:

a plurality of circuit devices arranged on a semiconductor substrate to form a contoured cell, wherein a plurality of interconnections couple between the plurality of circuit devices;

a plurality of busing conductors that are coupled to the plurality of circuit devices wherein the plurality of busing conductors define the row positions of the contoured cell in a larger circuit, the plurality of busing conductors providing a voltage to at least one of the plurality of circuit devices;

a non-rectangular cell contour defined in relation to the outermost border of each of the plurality of circuit devices and each of the plurality of interconnections, wherein the outermost boundary of the cell contour of adjacent cells will abut when the larger circuit is assembled from the plurality of contoured cells,

wherein the plurality of busing conductors includes a first pair of parallel busing conductors, between which the circuit devices and interconnections are arranged, and wherein the non-rectangular contour semiconductor cell is arranged on the semiconductor substrate such that a circuit element including a second busing conductor is adjoined to the non-rectangular contour semiconductor cell along the cell contour such that the first pair of parallel busing conductors is parallel with the second busing conductor.

2. The non-rectangular contour semiconductor cell of claim 1, wherein at least two of the plurality of circuit devices are different sizes.

3. A library of non-rectangular contour semiconductor cells, comprising:

a plurality of non-rectangular contour semiconductor cells for arranging on a semiconductor substrate, wherein each of the non-rectangular contour semiconductor cells comprises

a plurality of circuit devices arranged on a semiconductor substrate to form a contoured cell, wherein a plurality of interconnections couple between the plurality of circuit devices;

a plurality of busing conductors that are coupled to the plurality of circuit devices wherein the plurality of busing conductors define the row positions of the contoured cell in a larger circuit, the plurality of busing conductors providing a voltage to at least one of the plurality of circuit devices;

a non-rectangular cell contour defined in relation to the outermost border of each of the plurality of circuit devices and each of the plurality of interconnections, wherein the outermost boundary of the cell contour of adjacent cells will abut when the larger circuit is assembled from the plurality of contoured cells,

wherein the plurality of busing conductors includes a first pair of parallel busing conductors, between which the circuit devices and interconnections are arranged, and wherein the non-rectangular contour semiconductor cell is arranged on the semiconductor substrate such that a circuit element including a second busing conductor is adjoined to the non-rectangular contour semiconductor cell along the cell contour such that the first pair of parallel busing conductors is parallel with the second busing conductor.

4. The library of claim 3, wherein at least two of the plurality of circuit devices are different sizes.

5. A semiconductor circuit, comprising:

a plurality of non-rectangular contour semiconductor cells arranged on a semiconductor substrate, wherein each of the non-rectangular contour semiconductor cells comprises

a plurality of circuit devices arranged on a semiconductor substrate to form a contoured cell, wherein a plurality of interconnections couple between the plurality of circuit devices;

a plurality of busing conductors that are coupled to the plurality of circuit devices wherein the plurality of busing conductors define the row positions of the contoured cell in a larger circuit, the plurality of busing conductors providing a voltage to at least one of the plurality of circuit devices;

a non-rectangular cell contour defined in relation to the outermost border of each of the plurality of circuit devices and each of the plurality of interconnections, wherein the outermost boundary of the cell contour of adjacent cells will abut when the larger circuit is assembled from the plurality of contoured cells,

wherein the plurality of busing conductors includes a first pair of parallel busing conductors, between which the circuit devices and interconnections are arranged, and wherein the non-rectangular contour semiconductor cell is arranged on the semiconductor substrate such that a circuit element including a second busing conductor is adjoined to the non-rectangular contour semiconductor cell along the cell contour such that the first pair of parallel busing conductors is parallel with the second busing conductor.

6. The semiconductor circuit of claim 5, wherein at least two of the plurality of circuit devices are different sizes.