Enhancement-depletion logic based on Ge mosfets

• US 5,798,555 A
• Filed: 11/27/1996
• Issued: 08/25/1998
• Est. Priority Date: 11/27/1996
• Status: Expired due to Fees

• Current Assignee: Regents of the University of California (University of California)
• Original Assignee: Regents of the University of California (University of California)
• Inventors: DenBaars, Steven P., Mishra, Umesh Kumar
• Primary Examiner(s): WHITEHEAD JR, CARL W
• Application Number:
  US08/756,415
• Time in Patent Office: 636 Days
• Field of Search: 257/192, 257/410, 257/616, 257/347, 257/213, 257/289, 437/40, 437/22, 437/24, 437/57, 437/107, 437/132, 437/133, 437/976, 437/93, 117/90
• US Class Current: 257/410
• CPC Class Codes: H01L 21/02178 the material containing aluminium, e.g. Al2O3
• CPC Class Codes: H01L 21/02241 III-V semiconductor
• CPC Class Codes: H01L 21/28255 the insulator being formed after the semiconductor body, the semiconductor belonging to Group IV and not being elemental silicon, e.g. Ge, SiGe, SiGeC
• CPC Class Codes: H01L 21/31666 of AIII BV compounds
• CPC Class Codes: H01L 21/8256 the substrate being a semiconductor, using technologies not covered by one of groups H01L21/8206, H01L21/8213 , H01L21/822, H01L21/8252 and H01L21/8254 H01L21/8258 takes precedence
• CPC Class Codes: H01L 27/0605 integrated circuits made of compound material, e.g. AIIIBV
• CPC Class Codes: H01L 29/517 the insulating material comprising a metallic compound, e.g. metal oxide, metal silicate H01L29/518 takes precedence
• CPC Class Codes: H01L 29/66477 with an insulated gate, i.e. MISFET

Abstract

The present invention discloses a method of forming an oxide layer on a layer of germanium including the steps of depositing a layer of aluminum arsenide on the layer of germanium, of exposing the layer of aluminum arsenide to an oxidizing gas mixture so that the aluminum arsenide is oxidized to aluminum oxide, and of controlling excess arsenic released in the aluminum oxide by the exposing step, so as to ensure enhanced electrical properties in the aluminum oxide. The method is used to provide an insulating gate layer for a Ge field effect transistor by forming an oxide layer on Ge and controlling excess arsenic so as to maintain high resistivity in the oxide layer and to avoid the formation of interface surface states which degrade transistor performance. The method is also used to provide complementary metal-insulator-semiconductor logic devices based on the germanium field effect transistor.

Claims

1. A germanium field effect device, having a source and a drain, comprising:

a germanium channel layer;

a gate layer, the gate layer being an aluminum oxide layer, formed over the germanium channel layer from a deposited aluminum arsenide layer;

an arsenic controlling layer in contact with the gate layer for controlling excess arsenic atoms in the gate layer; and

electrodes respectively formed over the source, the drain and the gate layer.

2. The device of claim 1, wherein the arsenic controlling layer comprises an n-type layer deposited on the aluminum arsenide layer.

3. The device of claim 2, wherein the n-type layer is formed from gallium arsenide, aluminum gallium arsenide or indium gallium phosphide.

4. The device of claim 1, wherein the arsenic controlling layer comprises a semiconductor vacancy layer.

5. The device of claim 4, wherein the semiconductor vacancy layer is a low temperature growth layer of gallium arsenide deposited over the aluminum arsenide layer.

6. The device of claim 1, wherein the arsenic controlling layer comprises a semiconductor barrier layer deposited between the germanium channel layer and the aluminum arsenide layer for preventing the excess arsenic atoms from migrating into the germanium channel layer.

7. The device of claim 6, wherein the semiconductor barrier layer is formed from the group consisting of aluminum gallium arsenide and indium gallium phosphide.

8. A germanium field effect device having a source and a drain, comprising:

a germanium layer;

a gate layer, the gate layer being formed from hydrogenated aluminum oxide, formed over the germanium layer from a deposited aluminum arsenide layer; and

electrodes respectively formed over the source, the drain and the hydrogenated gate aluminum oxide layer.

9. A germanium complementary metal-insulator-semiconductor device, comprising:

a substrate;

a first transistor on the substrate, the first transistor comprising a first source, a first drain, an n-type germanium channel layer, the n-type germanium channel layer being in an intermediate conducting relationship with the first and second source, a first gate layer, the first gate layer being an aluminum oxide layer, the first gate layer being formed over the n-type germanium channel layer, and a first arsenic controlling layer in contact with the first gate layer for controlling excess arsenic atoms in the first gate layer; and

a second transistor on the substrate, the second transistor comprising a second source, a second drain, a p-type germanium channel layer, the p-type germanium channel layer being in an intermediate conducting relationship with the second source and the second gate, a second gate layer, the second gate layer being an aluminum oxide layer, the second gate layer being formed over the p-type germanium channel layer, and a second arsenic controlling layer in contact with the second gate layer for controlling excess arsenic atoms in the second gate layer.

10. The device of claim 9, wherein at least one of the first arsenic controlling layer and the second arsenic controlling layer comprises a vacancy semiconductor layer deposited over at least one of the first gate layer and the second layer respectively.

11. The device of claim 10, wherein the vacancy semiconductor layer comprises a layer of low temperature growth gallium arsenide.

12. The device of claim 9, wherein at least one of the first arsenic controlling layer and the second arsenic controlling layer comprises a semiconductor barrier layer deposited between at least either the n-type germanium channel layer and the first gate layer or the p-type germanium channel layer and the second gate layer, respectively.

13. The device of claim 12, wherein the semiconductor barrier layer is formed from the group consisting of aluminum gallium arsenide and indium gallium phosphide.

14. A germanium complementary metal-insulator-semiconductor device, comprising:

a substrate;

a first transistor on the substrate, the first transistor comprising a first source, a first drain, an n-type germanium channel layer, the n-type germanium channel layer being in an intermediate conducting relationship with the first source and the first drain, a first gate layer, the first gate layer being a hydrogenated aluminum oxide layer formed over the n-type germanium channel layer; and

a second transistor on the substrate, the second transistor comprising a second source, a second drain a p-type germanium channel layer, the p-type germanium channel layer being in an intermediate conducting relationship with the second source and the second drain, a second gate layer, the second gate layer being a hydrogenated aluminum oxide layer formed over the p-type germanium channel layer.