Ball grid array integrated circuit package which employs a flip chip integrated circuit and decoupling capacitors

• US 5,798,567 A
• Filed: 08/21/1997
• Issued: 08/25/1998
• Est. Priority Date: 08/21/1997
• Status: Expired due to Term

• Current Assignee: Avago Technologies General IP PTE Limited (Broadcom, Inc.)
• Original Assignee: Hewlett-Packard Company (HP Inc.)
• Inventors: Kelly, Michael G., Emad, Pirooz
• Primary Examiner(s): Saadat, Mahshid D.
• Assistant Examiner(s): CLARK, SHEILA V
• Application Number:
  US08/915,969
• Time in Patent Office: 369 Days
• Field of Search: 257/778, 257/691, 257/693, 257/686, 257/687, 257/723, 257/777, 257/724, 257/780
• US Class Current: 257/723
• CPC Class Codes: H01L 2224/16225 the item being non-metallic, e.g. insulating substrate with or without metallisation
• CPC Class Codes: H01L 2224/45144 Gold (Au) as principal constituent
• CPC Class Codes: H01L 2224/48091 Arched
• CPC Class Codes: H01L 2224/48227 connecting the wire to a bond pad of the item
• CPC Class Codes: H01L 2224/73253 Bump and layer connectors
• CPC Class Codes: H01L 23/13 characterised by the shape
• CPC Class Codes: H01L 23/49816 Spherical bumps on the substrate for external connection, e.g. ball grid arrays [BGA]
• CPC Class Codes: H01L 23/49827 Via connections through the substrates, e.g. pins going through the substrate, coaxial cables H01L23/49822, H01L23/49833, H01L23/4985, H01L23/49861 take precedence
• CPC Class Codes: H01L 23/50 for integrated circuit devices, e.g. power bus, number of leadsH01L23/482 - H01L23/498 take precedence
• CPC Class Codes: H01L 24/45 of an individual wire connector
• CPC Class Codes: H01L 24/48 of an individual wire connector
• CPC Class Codes: H01L 2924/00 Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
• CPC Class Codes: H01L 2924/00012 Relevant to the scope of the group, the symbol of which is combined with the symbol of this group
• CPC Class Codes: H01L 2924/00014 the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
• CPC Class Codes: H01L 2924/01078 Platinum [Pt]
• CPC Class Codes: H01L 2924/01079 Gold [Au]
• CPC Class Codes: H01L 2924/01322 Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
• CPC Class Codes: H01L 2924/14 Integrated circuits
• CPC Class Codes: H01L 2924/15311 being a ball array, e.g. BGA
• CPC Class Codes: H01L 2924/1532 the connection portion being formed on the die mounting surface of the substrate
• CPC Class Codes: H01L 2924/181 : Encapsulation
• CPC Class Codes: H01L 2924/19041 : being a capacitor
• CPC Class Codes: H01L 2924/19106 : in a mirrored arrangement on two different side of a common die mounting substrate
• CPC Class Codes: H05K 1/0231 : Capacitors or dielectric substances
• CPC Class Codes: H05K 2201/10477 : Inverted
• CPC Class Codes: H05K 2201/1053 : Mounted components directly electrically connected to each other, i.e. not via the PCB
• CPC Class Codes: H05K 2201/10734 : Ball grid array [BGA]; Bump grid array
• CPC Class Codes: H05K 3/3436 : having an array of bottom contacts, e.g. pad grid array or ball grid array components
• CPC Class Codes: Y02P 70/50 : Manufacturing or production processes characterised by the final manufactured product

Abstract

A ball grid array to integrated circuit interconnection. The interconnection includes a ball grid array substrate having a first surface and a second surface. The first surface comprising a plurality of substrate interconnection conductive pads. A power supply via connects a power supply conductive pad of the first surface to a first conductive area on the second surface. A ground via connects a ground conductive pad of the first surface to a second conductive area on the second surface. A decoupling capacitor connected between the first conductive area and the second conductive area. The interconnection further comprises an integrated circuit comprising a plurality of integrated circuit conductive pads. A plurality of smaller solder balls interconnect at least one of the integrated circuit conductive pads to at least one of the substrate interconnection conductive pads. A circuit board substrate is electrically interconnected by larger solder balls to the ball grid array substrate.

Claims

1. A ball grid array interconnection comprising:

a ball grid array substrate having a first surface and a second surface, the first surface comprising a plurality of substrate interconnection conductive pads;

at least one power supply via connecting a power supply conductive pad of the first surface to a first conductive area on the second surface;

at least one ground via connecting a ground conductive pad of the first surface to a second conductive area on the second surface;

at least one decoupling capacitor connected between the first conductive area and the second conductive area;

an integrated circuit comprising a plurality of integrated circuit conductive pads;

a plurality of smaller solder balls interconnecting at least one of the integrated circuit conductive pads to at least one of the substrate interconnection conductive pads; and

a circuit board substrate electrically interconnected by larger solder balls to the ball grid array substrate.

2. The ball grid array interconnection as recited in claim 1, wherein the solder bumps forming the electrical interconnection between the circuit board substrate and the ball grid array substrate are attached to the first surface of the ball grid array substrate.

3. The ball grid array interconnection as recited in claim 1, wherein the solder bumps forming the electrical interconnection between the circuit board substrate and the ball grid array substrate are attached to the second surface of the ball grid array substrate.

4. The ball grid array interconnection as recited in claim 1, wherein a minimum distance between the at least one decoupling capacitor and the integrated circuit is only limited by a distance between the integrated circuit and the second surface.

5. The ball grid array interconnection as recited in claim 2, wherein a conductive adhesive fills a space between the integrated circuit and the circuit board substrate.

6. The ball grid array interconnection as recited in claim 1, wherein a coupling loop is formed by the first conductive area connected to a power supply via, the power supply via connected to the power supply conductive pad, the power supply conductive pad connected to the integrated circuit, the integrated circuit connected to the ground conductive pad, the ground conductive pad connected to a ground via, the ground via connected to the second conductive area, and the second conductive area connected to the first conductive area through a coupling capacitor.

7. The ball grid array interconnection as recited in claim 6, wherein a length of the coupling loop is minimized.

8. The ball grid array interconnection as recited in claim 6, wherein an area encompassed by the coupling loop is minimized.