Switch mode sine wave driver for polyphase brushless permanent magnet motor

• US 5,798,623 A
• Filed: 02/12/1996
• Issued: 08/25/1998
• Est. Priority Date: 02/12/1996
• Status: Expired due to Term

• Current Assignee: Maxtor Corporation (Seagate Technology Holdings Plc)
• Original Assignee: Quantum Corporation (Chi Ko Investment Co., Ltd.)
• Inventors: El-Sadi, Ashraf I.
• Primary Examiner(s): SALATA, ANTHONY J
• Application Number:
  US08/598,584
• Time in Patent Office: 925 Days
• Field of Search: 318/254, 318/439, 318/138, 360/77.02, 360/77.04, 360/77.11, 360/78.06, 360/77.08, 388/805, 388/813, 388/820, 388/902, 388/905, 388/907.5
• US Class Current: 318/400.17
• CPC Class Codes: H02P 2209/07 Trapezoidal waveform
• CPC Class Codes: H02P 6/06 Arrangements for speed regulation of a single motor wherein the motor speed is measured and compared with a given physical value so as to adjust the motor speed
• CPC Class Codes: H02P 6/10 Arrangements for controlling torque ripple, e.g. providing reduced torque ripple
• CPC Class Codes: H02P 6/34 Modelling or simulation for control purposes

Abstract

A switch mode sine wave driver circuit selectively sources and sinks driving currents to and from a DC brushless motor in accordance with the substantially sinusoidal switched driving signals. A signal waveform monitoring circuit monitors electrical signals appearing the motor windings and puts out motor phase reference signals. A phase clock generator provides a motor-synchronized clock signal. A phase counter is clocked by the motor clock signal and is reset by the motor phase reference signals. The phase counter counts predetermined phase intervals and generates phase counts and phase polarity signals. A motor state decoder responds to the phase polarity signals by generating state control signals. Sine wave logic circuitry is addressed by the phase counts and puts out digital polyphase sine values for each one of the polyphases. A polyphase pulse width modulator circuit responds to the polyphase sine values by generating phase pulses having duty cycle duration controlled by the sine values. A logic decoder responds to the state control signals by decoding the phase pulses into phase driving pulses and by supplying the phase driving pulses to control a polyphase motor driver bridge circuit in order to rotate the motor.

Claims

1. A switch mode sine wave driver circuit for a multiple phase brushless permanent magnet motor comprises;

a signal waveform monitoring circuit for monitoring electrical signals appearing at plural motor phase windings of the motor for putting out phase reference signals;

phase clock generators responsive to the phase reference signals for providing plural phase motor-synchronized clock signals;

plural phase counters each being clocked by a respective one of the plural phase motor-synchronized clock signals and reset by the phase reference signals for counting motor phase counts of one of plural motor phases within motor phase intervals,

a single quadrant sine wave lookup logic circuit separately addressed by the motor phase counts for sequentially putting out digital polyphase raw sine values,

phase adjustment logic for adjusting the digital polyphase raw sine values in accordance with rotational position of the motor to provide digital polyphase adjusted sine values,

polyphase pulse width modulators responsive to the digital polyphase adjusted sine values for recurrently generating fixed amplitude signed phase pulses having duty cycle duration controlled by the digital polyphase adjusted sine values wherein the sum of durations of signed phase pulses equals zero;

and,

polyphase motor driver bridge circuitry for selectively sourcing and sinking driving currents to and from the plural motor windings in accordance with the fixed amplitude signed phase pulses in order to energize and rotate the motor with switched sine wave drive.

2. The switch mode sine wave driver circuit set forth in claim 1 wherein the multiple phase brushless permanent magnet motor comprises three stator phase windings U, V and W, and wherein the polyphase motor driver bridge circuitry selectively sources and sinks driving currents to and from the three stator phase windings U, V and W in accordance with the fixed amplitude signed phase pulses substantially in accordance with the relation:

space="preserve" listing-type="equation">sin(U)+sin(V)+sin(W)=0.

3. The switch mode sine wave driver circuit set forth in claim 2 wherein the signal waveform monitoring circuit monitors electrical signals appearing at the three stator phase windings U, V and W, of the motor for putting out a phase reference signal u, v, w for each motor phase winding U, V and W,

wherein the phase clock generators are responsive to the u, v and w phase reference signals for providing motor-synchronized clock signals;

wherein the plural phase counters comprise three counters wherein each counter is clocked by a corresponding motor clock signal and reset by a corresponding phase reference signal u, v, w for determining predetermined motor phase intervals and for generating separate phase counts and phase polarity signals for an interval of each motor phase signal u, v and w;

wherein the phase adjustment logic comprises motor state decoder means responsive to the phase polarity signals for generating state control signals;

wherein the single quadrant sine wave lookup logic circuit is addressed by the phase counts for putting out digital polyphase sine values for each motor phase interval;

wherein the phase adjustment logic further comprises logic decoder means responsive to the state control signals for decoding the phase pulses into switched phase sine wave driving pulses;

and wherein the polyphase motor driver bridge circuitry comprises a three phase driver bridge for selectively sourcing and sinking driving currents to and from the three phase motor windings U, V and W in accordance with the switched phase sine wave driving pulses in order to energize and rotate the motor.

4. The switch mode sine wave driver circuit set forth in claim 1 wherein the signal waveform monitoring circuit for monitoring electrical signals appearing at one of plural motor windings of the motor includes circuitry for monitoring actual rotational speed of the motor, and further comprising a motor speed regulation control loop including

comparison circuitry for comparing actual rotational speed of the motor against a reference motor speed value to generate a motor speed error value, and

pulse width modulation clock control circuitry responsive to the motor speed error value for adjusting clocking of the polyphase pulse width modulators with the motor speed error value to generate speed compensated switched sine wave drive current at the polyphase motor driver bridge circuitry.

5. The switch mode sine wave driver circuit set forth in claim 1 wherein the signal waveform monitoring circuit further includes zero crossing detection circuitry for detecting zero crossing sampling points of back EMF voltages induced across the plural motor windings during motor operation,

current sense and sample and hold circuitry for sampling and holding driving current values from the polyphase motor driver bridge circuitry at the zero crossing sampling points to provide an actual current value,

a differencing circuit for subtracting the actual current value from the motor speed error value in a differencing circuit to produce a current error value,

a compensation circuit for compensating the current error value to produce a compensated current error, and

a clock divider circuit for adjusting a clocking signal by a function of the compensated current error in order to control the polyphase pulse width modulators.

6. An on-chip switch mode sine wave driver circuit for a multiple phase brushless permanent magnet motor comprising:

a signal waveform monitoring circuit for monitoring electrical signals appearing across plural phase motor windings of the motor for putting out a phase reference signal for each motor phase;

a phase clock generator responsive to plural phase reference signals for providing a motor-synchronized clock signal;

plural phase counters clocked by the motor clock signal and reset by the phase reference signals for determining predetermined motor phase intervals and for generating phase counts and phase polarity signals for each motor phase interval;

motor state decoder means responsive to the phase polarity signals for generating state control signals;

a single sine wave lookup logic array sequentially addressed by the phase counts for putting out digital polyphase sine values for each motor phase interval;

polyphase pulse width modulators responsive to the digital polyphase sine values for generating phase pulses having duty cycle duration controlled by the sine values for each motor phase interval;

logic decoder means responsive to the state control signals for decoding the phase pulses into switched phase sine wave driving pulses; and

,

polyphase motor driver bridge circuitry for selectively sourcing and sinking driving currents to and from the plural phase motor windings in accordance with the switched phase sine wave driving signals in order to energize and rotate the motor with switched sine wave drive.

7. The on-chip switch mode sine wave driver circuit set forth in claim 6 wherein the multiple phase brushless permanent magnet motor comprises three electrical winding phases (U, V and W).

8. The on-chip switch mode sine wave driver circuit set forth in claim 7 wherein the polyphase motor driver bridge circuitry selectively sources and sinks driving currents to and from the plural phase motor windings in accordance with the switched phase sine wave driving signals in order to energize and rotate the motor with switched sine wave drive substantially in accordance with the relation:

space="preserve" listing-type="equation">sin(U)+sin(V)+sin(W)=0.

9. The on-chip switch mode sine wave driver circuit set forth in claim 6 wherein the signal waveform monitoring circuit detects and signals back EMF zero crossings of the electrical signals, and further comprising driving current sensing circuitry responsive to the zero crossings for sensing and holding driving currents supplied by the polyphase motor driver bridge circuit, speed error digital to analog conversion means responsive to the phase counter means for generating motor speed values, a difference amplifier for differencing the sensed and held driving currents from the motor speed values to produce a current command value, and an analog to digital converter for converting the current command value into a digital duty cycle value, and further comprising programmable duty cycle clock means modulated by the digital duty cycle value for clocking the polyphase pulse width modulation means in order to maintain and regulate motor speed at the predetermined angular velocity.

10. The on-chip switch mode sine wave driver set forth in claim 6 wherein the single sine wave lookup logic array puts out digital polyphase sine values over a range of ninety degrees of motor rotation and further comprising select, multiplex, adder circuitry responsive to the motor state decoder for selecting, multiplexing and adding selected ones of said digital polyphase sine values to provide sine values over a range of 360 degrees of motor rotation for each of the phases of the multiple phase brushless permanent magnet motor.

11. A switch mode sine wave driver circuit for a polyphase brushless DC motor having plural phase stator coils driven from a single polarity current supply in accordance with polyphase sinusoidally switched driving signals, the driver comprising:

a polyphase motor driver bridge circuit for selectively sourcing and sinking polyphase driving currents in accordance with the substantially sinusoidally switched driving signals from the single current supply through selected combinations of the plural phase stator coils to a current return to operate the motor at a predetermined angular velocity,

signal waveform monitoring means connected to the stator coils to monitor zero crossings of back EMF electrical signals appearing across the coils and for putting out motor phase reference signals,

phase clock generation means for generating a motor synchronous clock signal related to rotation of the motor,

plural phase counter means clocked by the motor synchronous clock, each phase counter means being separately reset by a corresponding one of the motor phase reference signals, for counting phase intervals of each polyphase of the motor during operation thereof and for generating phase counts and phase polarity signals,

state decoder means responsive to the phase polarity signals for generating state control signals,

sine wave logic circuitry addressed by the phase counts for putting out digital polyphase sine values for each one of the polyphases,

polyphase pulse width modulation means responsive to the polyphase sine values for generating phase pulses with duty cycles controlled by the sine values, and

logic decoder means responsive to the state control signals for decoding the phase pulses into phase driving pulses and for supplying the phase driving pulses to control the polyphase motor driver bridge circuit.

12. The switch mode sine wave driver circuit set forth in claim 11 wherein the polyphase motor comprises three electrical phases U, V and W.

13. The switch mode sine wave driver circuit set forth in claim 12 wherein the polyphase motor driver bridge circuit selectively sources and sinks driving currents to and from the plural motor windings in accordance with the phase driving pulses in order to energize and rotate the motor with switched sine wave drive substantially in accordance with the relation:

space="preserve" listing-type="equation">sin(U)+sin(V)+sin(W)=0.

14. The switch mode sine wave driver circuit set forth in claim 12 wherein the signal waveform monitoring means detects and signals zero crossings of the electrical signals, and further comprising driving current sensing circuitry responsive to the zero crossings for sensing and holding driving currents supplied by the polyphase motor driver bridge circuit, speed error digital to analog conversion means responsive to the phase counter means for generating motor speed values, a difference amplifier for differencing the sensed and held driving currents from the motor speed values to produce a current command value, and an analog to digital converter for converting the current command value into a digital duty cycle value, and further comprising programmable duty cycle clock means modulated by the digital duty cycle value for clocking the polyphase pulse width modulation means in order to maintain and regulate motor speed at the predetermined angular velocity.

15. The switch mode sine wave driver circuit set forth in claim 12 wherein the sine wave lookup logic circuitry puts out digital sine values over a range of ninety degrees of motor rotation and further comprising a select and adder circuit, and a select, multiplex, and adder circuit responsive to the state decoder means for selecting, multiplexing and adding selected ones of said digital polyphase sine values to provide sine values over a range of 360 degrees of motor rotation for each of the three electrical phases U, V and W.

16. A switch mode sine wave driver circuit for a three-phase brushless motor having 3ⁿ stator coils, where n is a whole integer equal to or greater than unity, driven by three-phase substantially sinusoidal switched driving signals and a rotor including a multiple-pole permanent magnet array having magnetic fields which interact with fields produced by the stator coils to rotate the rotor, the driver circuit comprising:

a motor driver bridge circuit for selectively sourcing and sinking bipolar driving currents to each one of the three phases in accordance with the substantially sinusoidal switched driving signals from a single current supply through selected combinations of the plurality of stator coils and through a current return to the supply to operate the motor at a predetermined angular velocity,

signal waveform monitoring means connected to the stator coils to monitor electrical signals appearing there across and for putting out motor phase reference signals marking zero crossings of each one of the three phases,

phase clock generation means responsive to motor rotational speed for generating a motor clock signal related to rotation of the motor,

three phase counters, each counter being clocked by the motor clock signal and reset by one of the motor phase reference signals, for counting phase intervals of each phase of the motor during operation thereof and for generating motor rotation phase counts and motor rotation phase polarity signals,

a state decoder responsive to the phase polarity signals for generating state control signals,

a table lookup sequencer responsive to the phase intervals generated by the three phase counters for sequentially presenting phase counts to a sine wave logic table,

the sine wave logic table for putting out digital sine values within one quadrant of rotation of the rotor for each one of the three phases,

three phase sine data registers for receiving and holding the digital sine values for the three phases,

selector means connected to receive, combine and select combinations of the digital sine values to provide processed digital sine values over a full rotation of the rotor,

asynchronous clocking means for generating a pulse width modulation clocking signal asynchronous to motor rotation,

three phase pulse width modulation means clocked by the pulse width modulation clocking signal and responsive to the processed digital sine values for generating sets of three phase pulses whose periods are fixed by the pulse width modulation clocking signal and whose duty cycles are controlled by the processed digital sine values,

logic decoder means responsive to the state control signals for decoding the phase pulses into phase driving control values and for supplying the phase driving control values to control the three phase motor driver bridge circuit thereby to selectively source and sink the bipolar driving currents to each one of the 3ⁿ stator coils.

17. A disk drive including a data storage disk rotated at a predetermined angular velocity by a multiple phase brushless permanent magnet disk spin motor, a data transducer in cooperative data transducing relationship with the data storage disk, and drive electromechanics for transferring blocks of data between a host computing environment and the data storage disk during disk drive operations, the disk drive further comprising an integrated circuit chip comprising a switch mode sine wave driver circuit for driving the multiple phase brushless permanent magnet disk spin motor, the chip including:

a signal waveform monitoring circuit for monitoring electrical signals appearing plural motor windings of the motor for putting out a phase reference signal for each motor phase;

a phase clock generator responsive to plural phase reference signals for providing a motor-synchronized clock signal;

phase counter means clocked by the motor clock signal and reset by the phase reference signals for determining predetermined motor phase intervals and for generating phase counts and phase polarity signals for each motor phase interval;

motor state decoder means responsive to the phase polarity signals for generating state control signals;

a single sine wave lookup logic array addressed by the phase counts for putting out sequential digital polyphase sine values for each motor phase interval;

polyphase pulse width modulators responsive to the sequential digital polyphase sine values for generating phase pulses having duty cycle duration controlled by the sine values;

logic decoder means responds to the state control signals for decoding the phase pulses into switched phase sine wave driving pulses; and

,

polyphase motor driver bridge circuitry for selectively sourcing and sinking driving currents to and from the plural motor windings in accordance with the switched phase sine wave driving signals in order to energize and rotate the disk spin motor with the switched phase sine wave driving pulses.

18. The disk drive set forth in claim 17 wherein the multiple phase brushless permanent magnet motor comprises three electrical phases (U, V and W) defined during each revolution of the motor.

19. The disk drive set forth in claim 18 wherein the polyphase motor driver bridge circuitry selectively sources and sinks driving currents from a single power supply to and from the plural motor windings in accordance with the switched phase sine wave driving signals in order to energize and rotate the motor with switched sine wave drive substantially in accordance with the relation:

space="preserve" listing-type="equation">sin(U)+sin(V)+sin(W)=0.

20. The disk drive set forth in claim 17 wherein the signal waveform monitoring circuit detects and signals zero crossings of the electrical signals, and further comprising driving current sensing circuitry responsive to the zero crossings for sensing and holding driving currents supplied by the polyphase motor driver bridge circuit, speed error digital to analog conversion means responsive to the phase counter means for generating motor speed values, a difference amplifier for differencing the sensed and held driving currents from the motor speed values to produce a current command value, and an analog to digital converter for converting the current command value into a digital duty cycle value, and further comprising programmable duty cycle clock means modulated by the digital duty cycle value for clocking the polyphase pulse width modulation means in order to maintain and regulate motor speed at the predetermined angular velocity.

21. The disk drive set forth in claim 17 wherein the single sine wave lookup logic array puts out digital polyphase sine values over a range of ninety degrees of motor rotation and further comprising a select and adder circuit and a select, multiplex, and adder circuit responsive to the motor state decoder for selecting, multiplexing and adding selected ones of said digital polyphase sine values to provide sine values over a range of 360 degrees of motor rotation.

22. The disk drive set forth in claim 17 further comprising an on-board disk drive microprocessor connected to the switch mode sine wave driver circuit chip for determining an at-rest position of the motor and for loading start up phase values into the phase counter means for starting up rotation of the disk spin motor in a controlled direction of rotation.

23. A method for energizing and rotating a brushless permanent magnet motor with switched sine wave drive current, comprising the steps of:

monitoring electrical signals appearing at plural motor windings with a signal waveform monitoring circuit and putting out a phase reference signal for each motor phase;

providing a motor-synchronized clock signal from a phase clock generator responsive to plural phase reference signals;

determining predetermined motor phase intervals and generating phase counts and phase polarity signals for each motor phase interval by clocking a phase counter means with the motor clock signal and by resetting the phase counter means with the phase reference signals;

generating state control signals with motor state decoder means responsive to the phase polarity signals;

putting out digital polyphase sine values for each motor phase interval sequentially from a single sine wave lookup logic array addressed by the phase counts for each motor phase interval;

generating phase pulses having duty cycle duration controlled by the sine values with polyphase pulse width modulators responsive to the digital polyphase sine values;

decoding the phase pulses into switched phase sine wave driving pulses with logic decoder means responds to the state control signals; and

,

selectively sourcing and sinking driving currents to and from the plural motor windings in accordance with the switched phase sine wave driving signals with polyphase motor driver bridge circuitry in order to energize and rotate the motor with the switched sine wave drive current.

24. The method set forth in claim 23 comprising the further steps of:

monitoring actual motor speed of the motor,

comparing actual motor speed of the motor against a reference motor speed value to generate a motor speed error value, and

controlling the polyphase pulse width modulators with the motor speed error value to generate speed compensated switched sine wave drive current at the polyphase motor driver bridge circuitry in order to maintain a desired speed of the motor.

25. The method set forth in claim 24 comprising the further steps of

detecting zero crossing sampling points of voltages across the plural motor windings with the signal waveform monitoring circuit,

sampling and holding driving current values from the polyphase motor driver bridge circuitry at the zero crossing sampling points to develop an actual current value,

subtracting the actual current value from the motor speed error value in a differencing circuit to produce a current error value,

compensating the current error value to produce a compensated current error, and

modulating a pulse width modulator clocking signal by the compensated current error in order to control the polyphase pulse width modulators.