Source-coupled logic with reference controlled inputs
First Claim
1. An MOSFET, reference controlled, source-coupled logic circuit for connection between a first power bus and a second power bus having a substantially constant potential difference between the buses, the logic circuit comprising:
- (a) a pair of MOSFET input transistors each having a source and an output and connected in a source-coupled arrangement, a first one of the input transistors having a gate forming a logic circuit input and the other input transistor having a gate connected to an external bias circuit shared by other logic circuits, each input transistor having a threshold voltage VT ;
(b) first and second pull-up resistive circuit elements each connected between the output of a respective different one of the input transistors and the first power bus;
(c) at least one output transistor connected as a source-follower, the output transistor having an input connected to the output of one of the input transistors and having an output forming a circuit output, said output transistor having a logic low output voltage VOL with respect to the second power bus; and
(d) a transistor, for conveying a substantially constant current, connected between the coupled input transistor sources and the second power bus and having an input connected to said bias circuit shared by multiple logic circuits, the constant current being controlled by the bias circuit and having a drain to source voltage at saturation VDSSAT and wherein VOL is substantially equal to VDSSAT +VT.
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Abstract
This invention relates to source-coupled logic (SCL) which is a functional derivative of emitter-coupled logic (ECL). ECL is widely recognized as having the characteristics of high speed (low propagation delay) and low power supply noise generation. The SCL of the prior art succeeds at maintaining and improving the low noise characteristics of this architecture but does not fulfill the promise of high speed that one would expect from a current-mode logic. In addition, it uses a differential form of logic that is not as flexible and easy-to-use as a reference controlled or "single-ended" logic. The SCL disclosed here has the desired high speed properties and maintains the ease of use that is a property of reference controlled ECL. In addition, the reference controlled SCL of this invention provides new capabilities that make it even more flexible than ECL in generating logical switching functions.
75 Citations
20 Claims
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1. An MOSFET, reference controlled, source-coupled logic circuit for connection between a first power bus and a second power bus having a substantially constant potential difference between the buses, the logic circuit comprising:
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(a) a pair of MOSFET input transistors each having a source and an output and connected in a source-coupled arrangement, a first one of the input transistors having a gate forming a logic circuit input and the other input transistor having a gate connected to an external bias circuit shared by other logic circuits, each input transistor having a threshold voltage VT ; (b) first and second pull-up resistive circuit elements each connected between the output of a respective different one of the input transistors and the first power bus; (c) at least one output transistor connected as a source-follower, the output transistor having an input connected to the output of one of the input transistors and having an output forming a circuit output, said output transistor having a logic low output voltage VOL with respect to the second power bus; and (d) a transistor, for conveying a substantially constant current, connected between the coupled input transistor sources and the second power bus and having an input connected to said bias circuit shared by multiple logic circuits, the constant current being controlled by the bias circuit and having a drain to source voltage at saturation VDSSAT and wherein VOL is substantially equal to VDSSAT +VT. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18)
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19. An MOSFET, reference controlled, source-coupled logic circuit for connection between a first power bus and a second power bus having a substantially constant potential difference between the buses, the logic circuit comprising:
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(a) a pair of MOSFET input transistors each having a source and an output and connected in a source-coupled arrangement, a first one of the input transistors having a gate forming a logic circuit input and the other input transistor having a gate connected to an external bias circuit shared by other logic circuits; (b) first and second pull-up resistive circuit elements each connected between the output of a respective different one of the input transistors and the first power bus; (c) at least one output transistor connected as a source-follower, the output transistor having an input connected to the output of one of the input transistors and having an output forming a circuit output; (d) a transistor, for conveying a substantially constant current, connected between the coupled input transistor sources and the second power bus and having an input connected to said bias circuit shared by multiple logic circuits, the constant current being controlled by the bias circuit; and (e) an input buffer circuit connected to the logic circuit input and including a differential comparator circuit and a voltage shifting circuit for translating the logic voltage levels applied to the input buffer circuit to logic levels compatible with said logic circuit.
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20. An MOSFET, reference controlled, source-coupled logic circuit for connection between a first power bus and a second power bus having a substantially constant potential difference between the buses, the logic circuit comprising:
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(a) a pair of MOSFET input transistors each having a source and an output and connected in a source-coupled arrangement, a first one of the input transistors having a gate forming a logic circuit input and the other input transistor having a gate connected to an external bias circuit shared by other logic circuits; (b) first and second pull-up resistive circuit elements each connected between the output of a respective different one of the input transistors and the first power bus; (c) at least one output transistor connected as a source-follower, the output transistor having an input connected to the output of one of the input transistors and having an output forming a circuit output; (d) a transistor, for conveying a substantially constant current, connected between the coupled input transistor sources and the second power bus and having an input connected to said bias circuit shared by multiple logic circuits, the constant current being controlled by the bias circuit; and (e) an output buffer circuit connected to the logic circuit output and including an SCL gate followed by a CMOS inverter for translating the logic voltage levels from the logic circuit output to other logic levels.
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Specification