Interpolating digital to analog converter architecture for improved spurious signal suppression

• US 5,798,724 A
• Filed: 02/14/1996
• Issued: 08/25/1998
• Est. Priority Date: 02/14/1996
• Status: Expired due to Term

• Current Assignee: Intersil Americas LLC (Renesas Electronics Corporation)
• Original Assignee: Harris Corporation (L3Harris Technologies, Inc.)
• Inventors: Myers, Brent
• Primary Examiner(s): Gaffin, Jeffrey A.
• Assistant Examiner(s): VICK, JASON
• Application Number:
  US08/601,401
• Time in Patent Office: 923 Days
• Field of Search: 341/159, 341/172, 341/118, 341/146, 341/190
• US Class Current: 341/146
• CPC Class Codes: H03M 1/0863 of switching transients, e.g. glitches
• CPC Class Codes: H03M 1/68 with conversions of different sensitivity, i.e. one conversion relating to the more significant digital bits and another conversion to the less significant bits
• CPC Class Codes: H03M 1/804 with charge redistribution

Abstract

A digital-to-analog conversion method and interpolating digital-to-analog converter for a data modulation system which reduces the spurious energy content of the output signal by an order of magnitude to thereby permit use of a less complex reconstruction filter to smooth the analog output. The process is a two step charge redistribution with feedback to interpolate between samples. DC offset is minimized by using double sampling techniques which permit a fully held signal between interpolation samples. A first conversion stage converts the first n bits of an N bit data signal received at an input rate to a first output value, and a second conversion stage converts the remainder of the N bits and combines signals from the two conversion stages to provide a combined output to an interpolation stage which provides an interpolated output at an interpolation output rate. A feedback circuit provides the interpolated output to an input of the second conversion stage.

Claims

1. A multistage charge redistribution digital to analog converter (DAC) comprising a filter network which has a network data conversion stage integral with an interpolation stage for improving suppression of spurious signals in an input signal to the DAC, said interpolation stage being clocked at a rate which is a multiple of the input rate of the DAC input signal, and for feeding back an output therefrom to said network data conversion stage to smooth an analog signal output from the DAC.

2. The DAC of claim 1 further comprising a prior data conversion stage for receiving the input signal to the DAC and for converting n bits of an N bit input signal to the DAC to a first output value which is provided to said network data conversion stage.

3. The DAC of claim 2 wherein said network data conversion stage is for converting the remaining bits of the N bit input signal to a second output value and for combining the first and second output values to provide a combined output value.

4. The DAC of claim 3 wherein said interpolation stage comprises a switched-capacitor filter for receiving the combined output value and providing an interpolated output at an interpolation rate which is said multiple times the input rate.

5. The DAC of claim 1 wherein said interpolation stage comprises a first operational amplifier and first and second switched-capacitors in parallel paths connecting an input and output of said first operational amplifier.

6. The DAC of claim 5 wherein said interpolation stage is connected to said network data conversion stage through a third switched-capacitor.

7. A digital to analog converter (DAC) for converting an N bit data signal received at an input rate to an analog signal in which spurious energy in the received data signal is reduced in the analog signal, the converter comprising:

a first conversion stage for converting n bits of an N bit data signal received at an input rate to a first output value;

a filter network comprising,

a second conversion stage for converting the remainder of the N bits in the data signal to a second output value, and for combining the first and second output values into a combined output value,

an interpolation stage for receiving the combined output value from said second conversion stage and for providing an interpolated output at an interpolation output rate which is a multiple of the input rate, and

a feedback circuit for feeding back the interpolated output from said interpolation stage to said second conversion stage,

whereby the interpolated output is the analog signal with reduced spurious energy.

8. The DAC of claim 7 wherein said feedback circuit comprises a capacitor which, in conjunction with said second conversion stage, forms a complex pole for providing an interpolated output.

9. The DAC of claim 7 wherein said interpolation stage comprises a first operational amplifier and first and second switched-capacitors in parallel paths connecting an input and output of said first operational amplifier.

10. The DAC of claim 9 wherein said interpolation stage is connected to said second conversion stage through a third switched-capacitor.

11. A method of reducing spurious energy in an analog signal which is output from a digital to analog converter (DAC) which converts an N bit data signal received at an input rate to an analog signal, the method comprising the steps of:

(a) converting in a first conversion stage n bits of an N bit data signal received at an input rate to a first output value;

(b) combining in a second conversion stage the remainder of the N bits in the data signal with the first output value to provide an amplitude value output;

(c) providing an interpolated amplitude output from an interpolation stage which interpolates the amplitude value output at an interpolation output rate which is a multiple of the input rate; and

(d) feeding back the interpolated amplitude output to an input to the second conversion stage,

whereby spurious energy in the interpolated amplitude output is reduced from that obtained by a direct conversion of the data signal.

12. The method of claim 11 wherein the feedback step comprises the step of forming a complex pole.