Interrupt system

• US 5,798,901 A
• Filed: 05/12/1997
• Issued: 08/25/1998
• Est. Priority Date: 08/22/1995
• Status: Expired due to Term

• Current Assignee: Firstpoint Contact Technologies, LLC (Alvaria Incorporated)
• Original Assignee: Rockwell International Corporation
• Inventors: Signaigo, Robert C.
• Primary Examiner(s): Leja, Ronald W.
• Application Number:
  US08/854,865
• Time in Patent Office: 470 Days
• Field of Search: 361/62-66, 361/115, 361/171, 361/191, 307/31, 307/38, 307/126, 307/132 E, 307/140, 340/825.71, 340/825.77, 340/825.06, 340/825.07, 340/825.08, 340/310.06, 340/644, 395/284, 395/285, 395/289-292, 395/297, 395/304, 395/828, 395/865, 395/727, 395/733, 395/736
• US Class Current: 361/64
• CPC Class Codes: G05B 19/042 using digital processors G05B19/05 takes precedence
• CPC Class Codes: G05B 2219/25416 Interrupt

Abstract

An interrupt system (10) having a plurality of electrical devices (12) having a time frame in which to examine an interrupt acknowledgement cycle, first and second lines (14 and 16) electrically connected to each of the electrical devices (12), a device (18) for issuing an interrupt signal on the first line (14), with said devices (12) determining during its time frame whether the cycle is intended for itself, and selected electrical devices (12) asserting a common acknowledgement signal on the second line (16) indicating the cycle is being serviced, such that removal of any electrical device (12) does not compromise the system interrupt capability.

Claims

1. An interrupt system, comprising:

a plurality of electrical devices, each electrically operatively coupled to a first line and a second line in a parallel arrangement;

means for issuing an interrupt signal on the first line such that each electrical device receives the interrupt signal;

each electrical device configured to determine whether the interrupt signal received on the first line is intended for itself and respond thereto during an interrupt acknowledgment cycle, by asserting a common interrupt acknowledgement signal on the second line, if the interrupt signal was intended for itself;

a plurality of discrete time frames each having a predetermined length and located at a predetermined position within the interrupt acknowledgment cycle, each time frame corresponding to one electrical device of the plurality of electrical devices;

each electrical device asserting the common interrupt acknowledgment signal on the second line only during its time frame if the interrupt signal was intended for itself, said assertion of the common interrupt acknowledgment signal indicating that the interrupt acknowledgment cycle is being serviced such that removal of any one of the electrical devices does not prevent remaining electrical devices from receiving the interrupt signal and asserting the common interrupt acknowledgment signal if the interrupt signal was intended for itself.

2. The interrupt system according to claim 1 wherein each time frame corresponding to each electrical device is arranged in a non-overlapping sequential manner within the interrupt acknowledgment cycle.

3. The interrupt system according to claim 1 wherein each of the electrical devices is configured to respond to the interrupt signal during its time frame and is prevented from responding during a time frame assigned to a another electrical device.

4. The interrupt system according to claim 1 wherein each of the electrical devices receives the interrupt signal at the same time, and if the interrupt signal was intended for itself, the electrical device asserts the common interrupt acknowledgment signal at a different time from the time that any other electrical device asserts the common interrupt acknowledgment signal in its time frame within the interrupt acknowledgment cycle.