Method and apparatus for sizing buffers to provide minimal skew

• US 5,798,935 A
• Filed: 07/01/1996
• Issued: 08/25/1998
• Est. Priority Date: 07/01/1996
• Status: Expired due to Fees

• Current Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Original Assignee: Sun Microsystems Incorporated (Oracle Corporation)
• Inventors: Lin, Yuan-Jung, Pance, Aleksandar, Doreswamy, Manjunath
• Primary Examiner(s): Teska, Kevin J.
• Assistant Examiner(s): ROBERTS, ANDREW S
• Application Number:
  US08/673,041
• Time in Patent Office: 785 Days
• Field of Search: 371/1, 395/551, 395/552, 395/555, 395/556, 395/557, 395/558, 395/770, 395/607, 395/613, 395/500, 364/488-491
• US Class Current: 716/114
• CPC Class Codes: G06F 30/394 Routing G06F30/396 takes precedence

Abstract

Disclosed is a system for automatically generating tables of buffer data which can be used during integrated circuit design to select appropriate buffers for signal distribution networks. The generated buffer data may be used by automated place and route systems to generate signal distribution networks having minimal skew. In the table, incrementally varying network features or criteria are provided (in the form of a table or list for example). Examples of such features include the length of a line connecting an L4 buffer to one or more L5 buffers and the number of L5 buffers driven by a single L4 buffer. For each incremental value of the network feature or features, one or more buffer types is specified. These buffer types have been previously modeled in the environment of the incremental value of the network features and found to meet certain criteria necessary to minimize skew. If when designing a signal distribution network the designer (or design tool) chooses L4 buffers from the proper locations on the table, then skew should be minimized.

Claims

1. A method of generating buffer data for use in selecting suitable buffer types for placement at given locations in a signal distribution network during the design of a microprocessor, the suitable buffer types being selected to minimize skew in the signal distribution network, the method comprising the following steps:

providing a collection of buffer types available for placement at given locations within a first stage of the signal distribution network;

providing a skew budget for signal propagation between the first stage and a next adjacent stage of said signal distribution network;

for said first stage of the signal distribution network, providing a range of incrementally varying values of at least one feature affecting skew, at least one of said incrementally varying values depending on at least one of said given locations within said first stage; and

automatically selecting, for each of said incrementally varying values, one or more suitable buffer types from among the collection of buffer types, which suitable buffer types are selected to meet the skew budget.

2. The method of claim 1, wherein the signal distribution network is a clock distribution network.

3. The method of claim 2, wherein the step of providing a collection of buffer types provides multiple L4 buffers.

4. The method of claim 1, wherein the step of providing a range of incrementally varying values provides incrementally varying values of a line length connecting buffers of said first stage to buffers of said next adjacent stage of the signal distribution network.

5. The method of claim 1, wherein the step of providing a range of incrementally varying values provides incrementally varying numbers of next adjacent stage buffers being driven by a buffer in the first stage.

6. The method of claim 1, wherein the step of automatically selecting one or more suitable buffer types generates a table of suitable buffer types for specified combinations of (i) line length connecting buffers of said first stage to buffers of said next adjacent stage of the signal distribution network, and (ii) numbers of next adjacent stage buffers being driven by a buffer in the first stage.

7. The method of claim 6, wherein the signal distribution network is a clock distribution network and wherein said first stage to buffers are L4 buffers and said next adjacent stage buffers are L5 buffers.

8. The method of claim 6, further comprising a step of determining for a given buffer type whether that buffer meets the skew budget for certain combinations of line length and number of next adjacent stage buffers, which step of determining includes, for a specified number of next adjacent stage buffers, the following steps:

identifying a right margin, said right margin representing a maximum acceptable line length from said first buffer to a specified number of next level buffers, said given buffer type, when connected to a line of the maximum acceptable line length, having a right margin delay of no more than about one or more of (a) a maximum high to low propagation delay from the output of the first buffer to the output of a next level buffer and (b) a maximum low to high propagation delay from the output of the first buffer to the output of a next level buffer; and

identifying a left margin, said left margin representing a minimum acceptable line length from said first buffer to a specified number of next level buffers, said given buffer type, when connected to a line of the minimum acceptable line length, having a left margin delay of at least about one or more of (c) a minimum high to low propagation delay from the output of the first buffer to the output of a next level buffer and (d) a minimum low to high propagation delay from the output of the first buffer to the output of a next level buffer.

9. The method of claim 8, wherein at least one of the steps of identifying the right margin and identifying the left margin is performed by a binary search algorithm.

10. The method of claim 8, wherein the steps of identifying the right margin and identifying the left margin further include steps of ensuring that said given buffer type, when connected to a line of the maximum acceptable line length, has no more than a maximum signal rise time and a maximum signal fall time.

11. A system for generating buffer data for use in selecting suitable buffer types for placement at given locations in a signal distribution network during the design of a microprocessor, the suitable buffer types being selected to minimize skew in the signal distribution network, the system comprising:

an input interface for accepting as input parameters (i) a collection of buffer types available for placement at given locations within a first stage of the signal distribution network, (ii) a skew budget for signal propagation between the first stage and a next adjacent stage of said signal distribution network;

(iii) a range of incrementally varying values of at least one feature affecting skew, at least one of said incrementally varying values depending on at least one of said given locations within said first stage; and

a computational module for automatically selecting, for each of said incrementally varying values, one or more suitable buffer types from among the collection of buffer types, which suitable buffer types are selected to meet the skew budget.

12. The system of claim 11, wherein the signal distribution network is a clock distribution network.

13. The system of claim 12, wherein the input interface accepts L4 buffers as the collection of buffer types.

14. The system of claim 11, wherein the input interface accepts as a range of incrementally varying values incrementally varying values of a line length connecting buffers of said first stage to buffers of said next adjacent stage of the signal distribution network.

15. The system of claim 11, wherein the input interface accepts as a range of incrementally varying values incrementally varying numbers of next adjacent stage buffers being driven by a buffer in the first stage.

16. The system of claim 11, wherein the computational module automatically generates a table of suitable buffer types for specified combinations of (i) line length connecting buffers of said first stage to buffers of said next adjacent stage of the signal distribution network, and (ii) numbers of next adjacent stage buffers being driven by a buffer in the first stage.

17. The system of claim 16, wherein the signal distribution network is a clock distribution network and wherein said first stage to buffers are L4 buffers and said next adjacent stage buffers are L5 buffers.

18. The system of claim 16, wherein the computational module determines for a given buffer type whether that buffer meets the skew budget for certain combinations of line length and number of next adjacent stage buffers, and wherein the computational module determines this for a specified number of next adjacent stage buffers by

identifying a right margin, said right margin representing a maximum acceptable line length from said first buffer to a specified number of next level buffers, said given buffer type, when connected to a line of the maximum acceptable line length, having a right margin delay of no more than about one or more of (a) a maximum high to low propagation delay from the output of the first buffer to the output of a next level buffer and (b) a maximum low to high propagation delay from the output of the first buffer to the output of a next level buffer;

and

identifying a left margin, said left margin representing a minimum acceptable line length from said first buffer to a specified number of next level buffers, said given buffer type, when connected to a line of the minimum acceptable line length, having a left margin delay of at least about one or more of (c) a minimum high to low propagation delay from the output of the first buffer to the output of a next level buffer and (d) a minimum low to high propagation delay from the output of the first buffer to the output of a next level buffer.

19. The system of claim 18, wherein at least one of the right margin and the left margin are identified by the computational module through a binary search algorithm.

20. The system of claim 18, wherein the computational module when identifying the right margin and the left margin ensures that said given buffer type, when connected to a line of the maximum acceptable line length, has no more than a maximum signal rise time and a maximum signal fall time.

21. The system of claim 11, further comprising an output interface which presents a table of suitable buffer types in a format that can be used by a clock buffer insertion tool in the design of an integrated circuit.

22. The system of claim 11, further comprising a display for displaying a layout of said signal distribution network.

23. The system of claim 11, wherein said computational module is provided on a computer having one or more input and output devices, a display device, a data storage device, a central unit, and operational software for controlling said central processing unit.

24. A machine readable medium storing program instructions for generating buffer data for use in selecting suitable buffer types for placement at given locations in a signal distribution network during the design of a microprocessor, the suitable buffer types being selected to minimize skew in the signal distribution network, the machine readable medium comprising instructions for performing the following steps:

providing a collection of buffer types available for placement at given locations within a first stage of the signal distribution network;

providing a skew budget for signal propagation between the first stage and a next adjacent stage of said signal distribution network;

for said first stage of the signal distribution network, providing a range of incrementally varying values of at least one feature affecting skew, at least one of said incrementally varying values depending on at least one of said given locations within said first stage; and

automatically selecting, for each of said incrementally varying values, one or more suitable buffer types from among the collection of buffer types, which suitable buffer types are selected to meet the skew budget.

25. The machine readable medium of claim 24, wherein the signal distribution network is a clock distribution network.

26. The machine readable medium of claim 25, wherein the instructions for providing a collection of buffer types provide for accepting multiple L4 buffers.

27. The machine readable medium of claim 24, wherein the instructions for automatically selecting one or more suitable buffer types generates a table of suitable buffer types for specified combinations of (i) line length connecting buffers of said first stage to buffers of said next adjacent stage of the signal distribution network, and (ii) numbers of next adjacent stage buffers being driven by a buffer in the first stage.

28. The machine readable medium of claim 27, further comprising instructions for determining, for a given buffer type, whether that buffer meets the skew budget for certain combinations of line length and number of next adjacent stage buffers, which instructions for determining include, for a specified number of next adjacent stage buffers, instructions for performing the following steps:

identifying a right margin, said right margin representing a maximum acceptable line length from said first buffer to a specified number of next level buffers, said given buffer type, when connected to a line of the maximum acceptable line length, having a right margin delay of no more than about one or more of (a) a maximum high to low propagation delay from the output of the first buffer to the output of a next level buffer and (b) a maximum low to high propagation delay from the output of the first buffer to the output of a next level buffer; and

identifying a left margin, said left margin representing a minimum acceptable line length from said first buffer to a specified number of next level buffers, said given buffer type, when connected to a line of the minimum acceptable line length, having a left margin delay of at least about one or more of (c) a minimum high to low propagation delay from the output of the first buffer to the output of a next level buffer and (d) a minimum low to high propagation delay from the output of the first buffer to the output of a next level buffer.

29. The machine readable medium of claim 27, wherein at least one of the steps of identifying the right margin and identifying the left margin is performed by a binary search algorithm.

30. The machine readable medium of claim 27, wherein the steps of identifying the right margin and identifying the left margin are implemented with instructions for performing steps of ensuring that said given buffer type, when connected to a line of the maximum acceptable line length, has no more than a maximum signal rise time and a maximum signal fall time.