Flash memory VDS compensation techiques to reduce programming variability

• US 5,798,966 A
• Filed: 03/31/1997
• Issued: 08/25/1998
• Est. Priority Date: 03/31/1997
• Status: Expired due to Term

• Current Assignee: Intel Corporation
• Original Assignee: Intel Corporation
• Inventors: Keeney, Stephen N.
• Primary Examiner(s): Nelms, David C.
• Assistant Examiner(s): PHAN, TRONG Q
• Application Number:
  US08/828,873
• Time in Patent Office: 512 Days
• Field of Search: 365/185.18, 365/185.26, 365/185.29, 365/185.33, 365/218
• US Class Current: 365/185.18
• CPC Class Codes: G11C 16/10 Programming or data input circuits
• CPC Class Codes: G11C 16/30 Power supply circuits

Abstract

A nonvolatile memory device. For one embodiment, the nonvolatile memory device includes a bit line, a source line, and a nonvolatile memory cell having a drain coupled to the bit line, a source coupled to the source line, a control gate, and a floating gate. The nonvolatile memory device also includes a source voltage generator circuit coupled to the source line and generating a source line voltage when programming the nonvolatile memory cell. The source voltage generator circuit varies the source line voltage based on a location of the nonvolatile memory cell in the memory array. The nonvolatile memory device may also include a drain voltage generator circuit coupled to the bit line and generating a bit line voltage when programming the nonvolatile memory cell. The drain voltage generator circuit varies the bit line voltage based on the location of the nonvolatile memory cell in the memory array.

Claims

1. A nonvolatile memory device comprising:

a memory array including a bit line, a source line, and a nonvolatile memory cell having a drain coupled to the bit line, a source coupled to the source line, a control gate, and a floating gate; and

a source voltage generator circuit coupled to the source line and generating a source line voltage when programming the nonvolatile memory cell, wherein the source voltage generator circuit varies the source line voltage based on a location of the nonvolatile memory cell in the memory array.

2. The nonvolatile memory device of claim 1, wherein the source line has a source line resistance between the source of the nonvolatile memory cell and the source voltage generator circuit, and the source voltage generator circuit varies the source line voltage to compensate for the source line resistance.

3. The nonvolatile memory device of claim 1, further comprising a drain voltage generator circuit coupled to the bit line and generating a bit line voltage when programming the nonvolatile memory cell, wherein the drain voltage generator circuit varies the bit line voltage based on the location of the nonvolatile memory cell in the memory array.

4. The nonvolatile memory device of claim 3, wherein the source line has a source line resistance between the source of the nonvolatile memory cell and the source voltage generator circuit, the bit line has a bit line resistance between a bit line voltage and the drain of the nonvolatile memory cell, the source voltage generator circuit varies the source line voltage to compensate for the source line resistance, and the drain voltage generator circuit varies the bit line voltage to compensate for the bit line resistance.

5. The nonvolatile memory device of claim 3, further comprising a control circuit coupled to the source voltage generator circuit and the drain voltage generator circuit, wherein the control circuit controls programming of the nonvolatile memory cell.

6. The nonvolatile memory device of claim 5, wherein the control circuit decodes an address of the nonvolatile memory cell to generate a first value and a second value, wherein the control circuit couples the first value to the source voltage generator circuit and the source voltage generator circuit generates the source line voltage in response to the first value, and wherein the control circuit couples the second value to the drain voltage generator circuit and the drain voltage generator circuit generates the bit line voltage in response to the second value.

7. The nonvolatile memory device of claim 1, wherein the memory array includes a plurality of bit lines and a plurality of nonvolatile memory cells each having a drain coupled to one of the bit lines, a source coupled to the source line, a control gate, and a floating gate, wherein the source voltage generator circuit further varies the source line voltage based on a number of the plurality of memory cells programmed at one time.

8. The nonvolatile memory device of claim 1, wherein the memory array includes a plurality of nonvolatile memory blocks each including a bit line, wherein the nonvolatile memory cell is included within a selected one of the nonvolatile memory blocks, and wherein the source voltage generator circuit varies the source line voltage based on an address of a selected nonvolatile memory block and a location of the nonvolatile memory cell in the selected nonvolatile memory block.

9. The nonvolatile memory device of claim 8, further comprising a drain voltage generator circuit coupled to the bit line and generating a bit line voltage when programming the nonvolatile memory cell, wherein the drain voltage generator circuit varies the bit line voltage based on the location of the nonvolatile memory cell in the selected nonvolatile memory block.

19. The nonvolatile memory device of claim 2, wherein the bit line has a bit line resistance and the source voltage generator varies the source line voltage to compensate for the bit line resistance.

20. The nonvolatile memory device of claim 19, further comprising a bit line voltage source coupled to the bit line, wherein the bit line resistance is between the bit line voltage source and the drain of the nonvolatile memory cell.

10. A nonvolatile memory device comprising:

a memory array including a bit line, a source line, and a nonvolatile memory cell having a drain coupled to the bit line, a source coupled to the source line, a control gate, and a floating gate; and

a drain voltage generator circuit coupled to the bit line and generating a bit line voltage when programming the nonvolatile memory cell, wherein the drain voltage generator circuit varies the bit line voltage based on the location of the nonvolatile memory cell in the memory array.

11. The nonvolatile memory device of claim 10, wherein the source line has a source line resistance between the source of the nonvolatile memory cell and a source line generator voltage, the bit line has a bit line resistance between a bit line voltage source and the drain of the nonvolatile memory cell, and the drain voltage generator circuit varies the bit line voltage to compensate for the source line resistance and the bit line resistance.

12. A nonvolatile memory device comprising:

a memory array including a plurality of bit lines, a source line, and a plurality of nonvolatile memory cells each having a drain coupled to one of the bit lines, a source coupled to the source line, a control gate, and a floating gate; and

a source voltage generator circuit coupled to the source line and generating a source line voltage when programming one of the nonvolatile memory cells, wherein the source voltage generator circuit varies the source line voltage based on the number of nonvolatile memory cells programmed at one time.

13. A nonvolatile memory device comprising:

a memory array including a plurality of bit lines, a source line, and a plurality of nonvolatile memory cells each having a drain coupled to one of the bit lines, a source coupled to the source line, a control gate, and a floating gate; and

a drain voltage generator circuit coupled to the bit line and generating a bit line voltage when programming one of the nonvolatile memory cells, wherein the drain voltage generator circuit varies the bit line voltage based on the number of nonvolatile memory cells programmed at one time.

14. A method for setting a source line voltage for a selected one of a plurality of nonvolatile memory cells, wherein the plurality of nonvolatile memory cells each have a drain coupled to a bit line having a bit line resistance and a source coupled to the source line having a source line resistance, the method comprising the steps of:

decoding an address of the selected nonvolatile memory cell to produce a decoded address; and

adjusting, in response to the decoded address, the source line voltage coupled to the source line to compensate for the bit line resistance and the source line resistance.

15. The method of claim 14, further comprising the step of determining a number of the nonvolatile memory cells to be programmed together with the selected nonvolatile memory cell, wherein the adjusting step further adjusts the source line voltage of the selected nonvolatile memory cell in response to the number of nonvolatile memory cells programmed together with the selected nonvolatile memory cell.

16. A method for setting a bit line voltage for a selected one of a plurality of nonvolatile memory cells, wherein the plurality of nonvolatile memory cells each have a drain coupled to a bit line having a bit line resistance and a source coupled to the source line having a source line resistance, the method comprising the steps of:

decoding an address of the selected nonvolatile memory cell to produce a decoded address; and

adjusting, in response to the decoded address, the bit line voltage of the bit line coupled to the selected memory cell to compensate for the bit line resistance and the source line resistance.

17. A method for setting a source line voltage and a bit line voltage for a selected one of a plurality of nonvolatile memory cells, wherein the plurality of nonvolatile memory cells each have a drain coupled to a bit line having a bit line resistance and a source coupled to the source line having a source line resistance, the method comprising the steps of:

decoding an address of the selected nonvolatile memory cell to produce a decoded address;

adjusting, in response to the decoded address, the source line voltage coupled to source line to compensate for the source line resistance; and

adjusting, in response to the decoded address, the bit line voltage for the bit line couple to the selected nonvolatile memory cell to compensate for the bit line resistance.

18. The method of claim 17, further comprising the step of determining a number of the nonvolatile memory cells to be programmed together with the selected nonvolatile memory cell, wherein the step of adjusting the source line voltage further adjusts the source line voltage of the selected nonvolatile memory cell in response to the number of nonvolatile memory cells programmed together with the selected nonvolatile memory cell.