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Flash memory VDS compensation techiques to reduce programming variability

  • US 5,798,966 A
  • Filed: 03/31/1997
  • Issued: 08/25/1998
  • Est. Priority Date: 03/31/1997
  • Status: Expired due to Term
First Claim
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1. A nonvolatile memory device comprising:

  • a memory array including a bit line, a source line, and a nonvolatile memory cell having a drain coupled to the bit line, a source coupled to the source line, a control gate, and a floating gate; and

    a source voltage generator circuit coupled to the source line and generating a source line voltage when programming the nonvolatile memory cell, wherein the source voltage generator circuit varies the source line voltage based on a location of the nonvolatile memory cell in the memory array.

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