Flash memory VDS compensation techiques to reduce programming variability
First Claim
1. A nonvolatile memory device comprising:
- a memory array including a bit line, a source line, and a nonvolatile memory cell having a drain coupled to the bit line, a source coupled to the source line, a control gate, and a floating gate; and
a source voltage generator circuit coupled to the source line and generating a source line voltage when programming the nonvolatile memory cell, wherein the source voltage generator circuit varies the source line voltage based on a location of the nonvolatile memory cell in the memory array.
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Accused Products
Abstract
A nonvolatile memory device. For one embodiment, the nonvolatile memory device includes a bit line, a source line, and a nonvolatile memory cell having a drain coupled to the bit line, a source coupled to the source line, a control gate, and a floating gate. The nonvolatile memory device also includes a source voltage generator circuit coupled to the source line and generating a source line voltage when programming the nonvolatile memory cell. The source voltage generator circuit varies the source line voltage based on a location of the nonvolatile memory cell in the memory array. The nonvolatile memory device may also include a drain voltage generator circuit coupled to the bit line and generating a bit line voltage when programming the nonvolatile memory cell. The drain voltage generator circuit varies the bit line voltage based on the location of the nonvolatile memory cell in the memory array.
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Citations
20 Claims
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1. A nonvolatile memory device comprising:
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a memory array including a bit line, a source line, and a nonvolatile memory cell having a drain coupled to the bit line, a source coupled to the source line, a control gate, and a floating gate; and a source voltage generator circuit coupled to the source line and generating a source line voltage when programming the nonvolatile memory cell, wherein the source voltage generator circuit varies the source line voltage based on a location of the nonvolatile memory cell in the memory array. - View Dependent Claims (2, 3, 4, 5, 6, 7, 8, 9, 19, 20)
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10. A nonvolatile memory device comprising:
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a memory array including a bit line, a source line, and a nonvolatile memory cell having a drain coupled to the bit line, a source coupled to the source line, a control gate, and a floating gate; and a drain voltage generator circuit coupled to the bit line and generating a bit line voltage when programming the nonvolatile memory cell, wherein the drain voltage generator circuit varies the bit line voltage based on the location of the nonvolatile memory cell in the memory array. - View Dependent Claims (11)
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12. A nonvolatile memory device comprising:
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a memory array including a plurality of bit lines, a source line, and a plurality of nonvolatile memory cells each having a drain coupled to one of the bit lines, a source coupled to the source line, a control gate, and a floating gate; and a source voltage generator circuit coupled to the source line and generating a source line voltage when programming one of the nonvolatile memory cells, wherein the source voltage generator circuit varies the source line voltage based on the number of nonvolatile memory cells programmed at one time.
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13. A nonvolatile memory device comprising:
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a memory array including a plurality of bit lines, a source line, and a plurality of nonvolatile memory cells each having a drain coupled to one of the bit lines, a source coupled to the source line, a control gate, and a floating gate; and a drain voltage generator circuit coupled to the bit line and generating a bit line voltage when programming one of the nonvolatile memory cells, wherein the drain voltage generator circuit varies the bit line voltage based on the number of nonvolatile memory cells programmed at one time.
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14. A method for setting a source line voltage for a selected one of a plurality of nonvolatile memory cells, wherein the plurality of nonvolatile memory cells each have a drain coupled to a bit line having a bit line resistance and a source coupled to the source line having a source line resistance, the method comprising the steps of:
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decoding an address of the selected nonvolatile memory cell to produce a decoded address; and adjusting, in response to the decoded address, the source line voltage coupled to the source line to compensate for the bit line resistance and the source line resistance. - View Dependent Claims (15)
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16. A method for setting a bit line voltage for a selected one of a plurality of nonvolatile memory cells, wherein the plurality of nonvolatile memory cells each have a drain coupled to a bit line having a bit line resistance and a source coupled to the source line having a source line resistance, the method comprising the steps of:
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decoding an address of the selected nonvolatile memory cell to produce a decoded address; and adjusting, in response to the decoded address, the bit line voltage of the bit line coupled to the selected memory cell to compensate for the bit line resistance and the source line resistance.
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17. A method for setting a source line voltage and a bit line voltage for a selected one of a plurality of nonvolatile memory cells, wherein the plurality of nonvolatile memory cells each have a drain coupled to a bit line having a bit line resistance and a source coupled to the source line having a source line resistance, the method comprising the steps of:
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decoding an address of the selected nonvolatile memory cell to produce a decoded address; adjusting, in response to the decoded address, the source line voltage coupled to source line to compensate for the source line resistance; and adjusting, in response to the decoded address, the bit line voltage for the bit line couple to the selected nonvolatile memory cell to compensate for the bit line resistance. - View Dependent Claims (18)
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Specification