Scalable multimedia network

• US 5,799,017 A
• Filed: 04/29/1996
• Issued: 08/25/1998
• Est. Priority Date: 05/19/1994
• Status: Expired due to Term

• Current Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Original Assignee: Cisco Technology, Inc. (Cisco Systems, Inc.)
• Inventors: Gupta, Dev Vrat, Stone, Alan E., Sharper, Craig A., Chen, Yu-Ren Brian
• Primary Examiner(s): Pham, Chi H.
• Assistant Examiner(s): NGO, RICKY QUOC
• Application Number:
  US08/639,633
• Time in Patent Office: 848 Days
• Field of Search: 370/465, 370/466, 370/470, 370/471, 370/474, 370/489, 370/401, 370/490, 370/463, 370/420, 370/421, 370/419, 370/447, 370/461, 370/462
• US Class Current: 370/419
• CPC Class Codes: H04L 12/2801 Broadband local area networks
• CPC Class Codes: H04L 12/2852 Metropolitan area networks
• CPC Class Codes: H04L 12/64 Hybrid switching systems
• CPC Class Codes: H04L 12/6402 Hybrid switching fabrics
• CPC Class Codes: H04L 2012/5612 Ring
• CPC Class Codes: H04L 2012/5613 Bus (including DQDB)
• CPC Class Codes: H04L 2012/5614 User Network Interface
• CPC Class Codes: H04L 2012/5615 Network termination, e.g. NT1, NT2, PBX
• CPC Class Codes: H04L 2012/5627 Fault tolerance and recovery
• CPC Class Codes: H04L 2012/5638 Services, e.g. multimedia, GOS, QOS
• CPC Class Codes: H04L 2012/5651 Priority, marking, classes
• CPC Class Codes: H04L 2012/5652 Cell construction, e.g. including header, packetisation, depacketisation, assembly, reassembly
• CPC Class Codes: H04L 2012/5679 Arbitration or scheduling
• CPC Class Codes: H04L 2012/6427 Subscriber Access Module; Concentrator; Group equipment
• CPC Class Codes: H04L 2012/6443 Network Node Interface, e.g. Routing, Path finding
• CPC Class Codes: H04L 2012/6448 Medium Access Control [MAC]
• CPC Class Codes: H04L 2012/6459 Multiplexing, e.g. TDMA, CDMA
• CPC Class Codes: H04L 2012/6464 Priority
• CPC Class Codes: H04L 2012/6483 Video, e.g. MPEG
• CPC Class Codes: H04L 2012/6486 Signalling Protocols
• CPC Class Codes: H04L 2012/6489 : Buffer Management, Threshold setting, Scheduling, Shaping
• CPC Class Codes: H04L 49/107 : using shared medium
• CPC Class Codes: H04L 65/1026 : at the edge
• CPC Class Codes: H04L 65/1036 : at the edge
• CPC Class Codes: H04L 65/1101 : Session protocols
• CPC Class Codes: H04L 69/08 : Protocols for interworking; Protocol conversion
• CPC Class Codes: H04L 9/40 : Network security protocols
• CPC Class Codes: H04N 21/6118 : involving cable transmission, e.g. using a cable modem
• CPC Class Codes: H04N 21/64707 : for transferring content from a first network to a second network, e.g. between IP and wireless
• CPC Class Codes: H04N 7/173 : with two-way working, e.g. subscriber sending a programme selection signal
• CPC Class Codes: H04N 7/17309 : Transmission or handling of upstream communications
• CPC Class Codes: H04N 7/17336 : Handling of requests in head-ends
• CPC Class Codes: H04N 7/17345 : Control of the passage of the selected programme
• CPC Class Codes: H04Q 11/0478 : Provisions for broadband connections

Abstract

A scalable Multimedia Network providing integrated networking of data, voice, video and image services over a variety of access facilities including metallic loops, fiber/coax or digital fiber is disclosed herein.

The SMN establishes customer initiated switched virtual circuits for all traffic types and directs them to the appropriate backbone network. The SMN is based on a distributed switching platform that enables carriers to economically provide service to a small number of customers and add capacity incrementally as the customer base increases. The platform has a protocol adaptation capability which permits communications between customer premises equipment and potentially incompatible backbone networks or network servers.

Claims

1. A communication interface device for providing an interface between a communication bus and a user of a communication service comprising:

a. a memory interface for storing digital information to and from the communication bus and user;

b. a backplane interface for receiving and transmitting digital information in the form of cells of N bits in length, to and from the bus;

said cells forming packets of different bit lengths;

c. a user interface for providing digital information to and from a user upon demand in any order designated by the user;

d. a processor interface for controlling the internal operation of the device and for allowing a processor to transmit and receive packets to and from the bus; and

e. an arbitrator responsive to a request bit received from among the set of said backplane interface, said user interface and said processor interface, such that one from said set is allowed to access said memory interface.

2. The device of claim 1 wherein the memory interface is connected to memory.

3. The device of claim 1 where N=64.

4. The device of claim 3 wherein the cells comprise a plurality of first cells having a first packet cell format and a plurality of second cells having a second packet cell format, any first cell having priority over any second cell in accessing the communication bus.

5. The device of claim 4 wherein the first packet cell format comprises a cell of 8 bytes arranged as follows:

four bytes provide a destination address for the packet;

two bytes contain data information; and

two bytes contain priority information, sequence information, signaling information and CRC information.

6. The device of claim 5 wherein the destination address is provided by fields within the four bytes as follows:

a. a three bit bus destination field;

b. an eight bit shelf destination field;

c. a five bit slot destination field; and

d. a sixteen bit port destination field

and the priority information, sequence information, signaling information, and CRC information are provided by fields within the two bytes as follows;

a. a two bit priority field;

b. a two bit sequence number field;

c. a two bit signaling field;

d. a one bit spare field;

e. a one bit signaling enable field;

f. a one bit large packet identification field;

g. a one bit end of packet identification field;

h. a one bit CRC error reported field; and

i. a five bit CRC field.

7. The device of claim 4 wherein the second packet cell format comprises cells of 8 bytes comprising:

a. a first cell wherein the bytes are arranged as follows;

four bytes provide a destination address for the packet;

two bytes provide a reserved word; and

two bytes provide priority, congestion control, and CRC information;

b. a last cell wherein the bytes are arranged as follows;

zero to six bytes provide data information, one byte provides a byte count for the packet, and one byte provides CRC information;

c. zero or more cells wherein there are 7 data bytes followed by one byte containing CRC information.

8. The device of claim 4 wherein the first cell contains fields comprising:

a. a three bit bus destination field;

b. an eight bit shelf destination field;

c. a five bit slot destination field;

d. a sixteen bit port and VCI index;

e. a sixteen bit reserved word field;

f. a two bit priority field;

g. a one bit forward congestion field;

h. a two bit backward congestion field;

i. a one bit discard eligibility field;

j. a one bit spare data field;

k. a one bit control/data field;

l. a one bit large packet identification field;

m. a one bit end of packet identification field;

n. a one bit CRC error reported field; and

o. a five bit CRC field.

9. A communication interface device for providing an interface between a communication bus and a user of a communication service comprising:

a memory interface circuit for storing and retrieving digital data to and from an external dynamic memory;

a backplane interface circuit for receiving and transmitting said digital data in the form of cells to and from said bus, said cells forming packets of different bit lengths;

a user interface circuit for receiving and transmitting said packets to and from said user in any order designated by said user;

a processor interface circuit for allowing an external microprocessor to control the internal operation of said device and to transmit and receive packets to and from said bus; and

an arbitrator circuit responsive to a request bit from among the set of said backplane interface circuit, said user interface circuit and said processor interface circuit, such that one circuit from said set is allowed access to said external dynamic memory.

10. The device of claim 9 wherein the cells comprise a plurality of first cells having a first packet cell format and a plurality of second cells having a second packet cell format, any first cell having priority over any second cell in accessing the communication bus.

11. The device of claim 10 wherein the first packet cell format comprises a cell of 8 bytes arranged as follows:

four bytes provide a destination address for the packet;

two bytes contain data information; and

two bytes contain priority information, sequence information, signaling information and CRC information.

12. The device of claim 11 wherein the destination address is provided by fields within the four bytes as follows:

a. a three bit bus destination field;

b. an eight bit shelf destination field;

c. a five bit slot destination field; and

d. a sixteen bit port destination field

and the priority information, sequence information, signaling information, and CRC information are provided by fields within the two bytes as follows;

a. a two bit priority field;

b. a two bit sequence number field;

c. a two bit signaling field;

d. a one bit spare field;

e. a one bit signaling enable field;

f. a one bit large packet identification field;

g. a one bit end of packet identification field;

h. a one bit CRC error reported field; and

i. a five bit CRC field.

13. The device of claim 9 wherein the second packet cell format comprises cells of 8 bytes comprising:

a. a first cell wherein the bytes are arranged as follows;

four bytes provide a destination address for the packet;

two bytes provide a reserved word; and

two bytes provide priority, congestion control, and CRC information;

b. a last cell wherein the bytes are arranged as follows;

zero to six bytes provide data information, one byte provides a byte count for the packet, and one byte provides CRC information;

c. zero or more cells wherein there are 7 data bytes followed by one byte containing CRC information.

14. The device of claim 13 wherein the first cell contains fields comprising:

a. a three bit bus destination field;

b. an eight bit shelf destination field;

c. a five bit slot destination field;

d. a sixteen bit port and VCI index;

e. a sixteen bit reserved word field;

f. a two bit priority field;

g. a one bit forward congestion field;

h. a two bit backward congestion field;

i. a one bit discard eligibility field;

j. a one bit spare data field;

k. a one bit control/data field;

l. a one bit large packet identification field;

m. a one bit end of packet identification field;

n. a one bit CRC error reported field; and

o. a five bit CRC field.

15. The device of claim 9 which in one mode monitors cells on the communication bus and in another mode contends for transmitting cells onto the communication bus.