Apparatus and method for interfacing between a communications channel and a processor for data transmission and reception

• US 5,799,064 A
• Filed: 08/31/1995
• Issued: 08/25/1998
• Est. Priority Date: 08/31/1995
• Status: Expired due to Term

• Current Assignee: CIF Licensing LLC
• Original Assignee: Motorola, Inc. (Motorola Solutions, Inc.)
• Inventors: Wortman, John Jr., Sridhar, Manickam R., Hoang, Minh
• Primary Examiner(s): Woo, Stella
• Application Number:
  US08/521,717
• Time in Patent Office: 1,090 Days
• Field of Search: 379/98, 379/93, 379/96, 379/97, 375/222, 375/377
• US Class Current: 379/93.06
• CPC Class Codes: H04M 11/06 Simultaneous speech and data transmission, e.g. telegraphic transmission over the same conductors

Abstract

An apparatus (101) and method for interfacing between a processor (103) and a communications channel (105), the processor operable in data terminal equipment (102) such as a computer having a communications application program, to provide for data transmission and reception over a communications channel (105), utilizing the computer processor without additional or redundant microprocessor or digital signal processor components. The apparatus and method provide for data transfer between the interface apparatus (101) and the communications channel (105) at a first, determinate frequency corresponding to a specific data transmission rate. The apparatus and method provide for data transfer between the interface apparatus (101) and the processor (103) at a second, indeterminate frequency, and provides for interim data storage in memory (115) between data transmission (or data reception) and data processing, such as modulation and demodulation, by the computer processor (103). The apparatus and method further provide for generating an interrupt signal to the processor to indicate the presence of received data for processing and the absence of digital data for transmission.

Claims

1. An interface apparatus for interfacing between a processor and a communications channel, the processor operable in data terminal equipment having a communications application program capable of performing modem functions of training, equalization, encoding, and decoding, the communications application program being responsive to interrupt signals from the interface apparatus the interface apparatus comprising:

a channel interface circuit coupleable to the communications channel to receive an incoming data signal and to transmit an outgoing data signal;

a memory;

a codec coupled to the memory and further coupled to the channel interface circuit to periodically sample the incoming data signal at a first determinate frequency to form a sequence of incoming sampled data and to transfer the sequence of incoming sampled data to the memory, and to receive a sequence of outgoing digital data from the memory and to convert the sequence of outgoing digital data to the outgoing data signal;

an interrupt signal generator responsive to data conditions in the memory to generate a first interrupt signal and to transmit the first interrupt signal to the processor, the first interrupt signal indicating one of a first and second data condition, the first condition being a presence in the memory of a first predetermined quantity of digital data for processing by the communications application program and the second condition being an absence of a second predetermined quantity of digital data stored in the memory for transmission on the channel, such that the communications application program can respond to the first condition by removing data from the memory to perform modem functions thereon and can respond to the second condition by writing data to the memory, the data having been processed by modem functions in the communications application program; and

an electromechanical interface circuit coupled to the memory, to the interrupt signal generator, and to the processor for data transfer between the processor and the memory and for transmission of the first interrupt signal to the processor.

2. The interface apparatus of claim 1, further comprising:

a status detector coupled to the memory and to the interrupt signal generator, further coupled to the channel interface circuit, the status detector responsive to detect a communications system failure, wherein in response to a communications system failure a connection with the communications channel is terminated.

3. The interface apparatus of claim 1 wherein the interrupt signal generator is further responsive to generate and send to the processor a second interrupt signal to indicate a presence of an incoming ring signal on the communications channel.

4. The interface apparatus of claim 3, further comprising:

a one-bit quantizer coupled to the channel interface circuit for detection of an incoming ring signal.

5. The interface apparatus of claim 4, wherein the memory includes a ring FIFO for receiving incoming sampled data which is detected as an incoming ring signal.

6. The interface apparatus of claim 1, wherein the first interrupt signal is generated by the interrupt signal generator at a second indeterminate frequency which is different than the first frequency.

7. The interface apparatus of claim 1, wherein the memory includes a hook FIFO for storage of pulse dial information to be transmitted on the channel as an outgoing data signal.

8. The interface apparatus of claim 1, wherein the memory includes a FIFO to store outgoing digital data that has been processed by the modem functions of the communications application program and that is to be transmitted on the channel as an outgoing digital data signal.

9. The interface apparatus of claim 8 wherein the FIFO to store outgoing digital data is large enough to store at least 18 samples of outgoing digital data.

10. The interface apparatus of claim 1, wherein the memory includes a receive sample FIFO for storing incoming sampled data to eventually be processed by the modem functions in the communications application program.

11. The interface apparatus of claim 10 wherein the receive sample FIFO is large enough to store at least 18 samples of outgoing digital data.

12. The interface apparatus of claim 1 wherein the channel interface circuit is a data access arrangement.

13. The interface apparatus of claim 12 wherein the communications system is further operable for a modem function.

14. The interface apparatus of claim 12 wherein the communications system is further operable for a telephone answering function.

15. The interface apparatus of claim 12 wherein the communications system is further operable for a speech processing function.

16. The interface apparatus of claim 1 wherein the channel interface circuit is a digital interface circuit.

17. The interface apparatus of claim 16 wherein the communications system is further operable for a terminal adapter function.

18. A method of interfacing between a processor and a communications channel for data reception, the processor operable in data terminal equipment having a communications application program, capable of performing modem functions of training, equalization, encoding, and decoding, the communications application program being responsive to interrupt signals, the method comprising the steps of:

(a) receiving a data signal from the communications channel to form a received data signal;

(b) periodically sampling the received data signal at a first determinate frequency to form a sequence of received sampled data;

(c) storing the sequence of received sampled data in a memory;

(d) generating an interrupt signal to the processor to indicate the presence of received sampled data in the memory; and

(e) periodically transferring at a second indeterminate frequency the received sampled data from the memory to the processor so that the communications application program executing thereon may process the received sampled data according to modem functions of the communications application program.

19. The method of claim 18, further comprising the steps of:

(f) receiving and detecting an incoming ring signal from the communications channel;

(g) informing the processor of the detected incoming ring signal so that the communications application program can retrieve corresponding retrieved sampled data from the memory and determine the validity of the ring signal therefrom.

20. The method of claim 19, wherein the detection of an incoming ring signal further comprises:

(f1) quantizing a voltage level of the incoming ring signal received from the communications channel to form digital ring information;

(f2) storing the digital ring information in a memory; and

(f3) periodically transferring at the second frequency the digital ring information from the memory to the processor in response to the interrupt signal.

21. The method of claim 18, further comprising:

(g) repeating steps (a) through (e), inclusive, until the data signal has ceased to be received.

22. A method of interfacing between a processor and a communications channel for data transmission, the processor operable in data terminal equipment having a communications application program, capable of performing modem functions of training, equalization, encoding, and decoding, the communications application program being responsive to interrupt signals, the method comprising the steps of:

(a) periodically transferring at a first frequency a sequence of digital data from the processor to a memory, the digital data from the processor having been processed by a modem function of the communications application program executing on the processor;

(b) storing the sequence of digital data in the memory;

(c) periodically transferring at a second frequency the sequence of digital data to a codec to generate an outgoing data signal;

(d) transmitting the outgoing data signal on the communications channel; and

(e) generating an interrupt signal to the processor to indicate that the memory is capable of having stored therein more digital data from the processor.

23. The method of claim 22, wherein step (d) further comprises:

(d1) generating off hook and dial signals;

(d2) storing the off hook and dial signals as digital information in memory; and

(d3) transmitting the off hook and dial signals on the channel prior to transmitting the outgoing data signal.

24. The method of claim 22, further comprising:

(f) detecting whether the sequence of digital data is pulse dialing information, and in the event that the sequence of digital data is pulse dialing information, transmitting corresponding dial pulses on the communications channel.

25. The method of claim 22, further comprising:

(g) repeating steps (a) through (e), inclusive, until a termination sequence of the digital data transferred from the processor has been transferred to memory and transmitted as the outgoing data signal on the communications channel.

26. The method of claim 22, further comprising:

(h) detecting an occurrence of a data capacity condition and, upon such detection, generating a status signal to reset the memory and to institute retraining procedures for the communications system.

27. The method of claim 22, further comprising:

(i) detecting an occurrence of a communications system failure and, upon such detection, generating a status signal to terminate a connection with the communications channel.

28. The method of claim 22 wherein the first frequency is an indeterminate frequency.

29. The method of claim 22 wherein the second frequency is a determinate frequency.

30. The method of claim 22 wherein the generating an interrupt signal step (e) further comprises generating the interrupt signal to the processor when the memory has been depleted to a predetermined level of storage of digital data.

31. A method of interfacing between a processor and a communications channel for data transmission and reception, the processor operable in data terminal equipment having a communications application program, capable of performing modem functions of training, equalization, encoding, and decoding, the communications application program being responsive to interrupt signals, the method comprising the steps of:

(a) receiving a data signal from the communications channel to form a received data signal;

(b) periodically sampling the received data signal at a first frequency to form a sequence of received sampled data;

(c) storing the sequence of received sampled data in a memory;

(d) periodically transferring at a second frequency the received sampled data from the memory to the processor;

(e) periodically transferring at the second frequency a sequence of digital data from the processor to a memory;

(f) storing the sequence of digital data in the memory;

(g) periodically transferring at the first frequency the sequence of digital data to a codec to generate an outgoing data signal;

(h) transmitting the outgoing data signal on the communications channel; and

(i) generating an interrupt signal to the processor indicating one of a first and second data condition, the first condition being a presence in the memory of a first predetermined quantity of digital data for processing by the communications application program and the second condition being an absence of a second predetermined quantity of digital data stored in the memory for transmission on the channel, such that the communications application program can respond to the first condition by removing data from the memory to perform modem functions thereon and can respond to the second condition by writing data to the memory, the data having been processed by modem functions in the communications application program.

32. The method of claim 31, further comprising:

(j) receiving and detecting an incoming ring signal from the communications channel.

33. The method of claim 32, wherein the detection of an incoming ring signal step (j) further comprises:

(j1) quantizing a voltage level of the incoming ring signal received from the communications channel to form digital ring information;

(j2) storing the digital ring information in a memory;

(j3) periodically transferring at the second frequency the digital ring information from the memory to the processor in response to the interrupt signal.

34. The method of claim 31, further comprising:

(k) detecting whether the sequence of digital data is pulse dialing information, and in the event that the sequence of digital data is pulse dialing information, transmitting corresponding dial pulses on the channel.

35. The method of claim 31, further comprising:

(l) repeating steps (a) through (d), and step (i), inclusive, until the data signal has ceased to be received; and

(m) repeating steps (e) through (i), inclusive, until a termination sequence of the digital data transferred from the processor has been transferred to memory and transmitted as the outgoing data signal on the communications channel.

36. The method of claim 31, further comprising:

(n) detecting an occurrence of a data capacity condition and, upon such detection, generating a status signal to reset the memory and to institute retraining procedures for the communications system.

37. The method of claim 31, further comprising:

(o) detecting an occurrence of a communications system failure and, upon such detection, generating a status signal to terminate a connection with the communications channel.

38. The method of claim 31, wherein steps (a) through (d), inclusive, occur simultaneously with steps (e) through (i), inclusive.

39. The method of claim 31, wherein step (h) further comprises:

(h1) generating off hook and dial signals;

(h2) storing the off hook and dial signals as digital information in memory; and

(h3) transmitting the off hook and dial signals on the communications channel prior to transmitting the outgoing data signal.

40. The method of claim 31 wherein the first frequency is a determinate frequency.

41. The method of claim 31 wherein the second frequency is an indeterminate frequency.

42. The method of claim 31 wherein the generating an interrupt signal step (i) further comprises:

generating the interrupt signal to the processor when the memory has reached a predetermined capacity of storage of received sampled data.

43. The method of claim 31 wherein the generating an interrupt signal step (i) further comprises:

generating the interrupt signal to the processor when the memory has been depleted to a predetermined level of storage of digital data.